Institute of Information Theory and Automation

List of publications

Books and chapters

  1. Honzík Petr, Bartosinski Roman, Daněk Martin, Kafka Leoš, Kohout Lukáš, Sýkora JaroslavVideo Processing: Foreground Recognition in the ASVP Platform , Smart Multicore Embedded Systems, p. 159-175 , Eds: Massimo T., Bertels K., Karlsson S., Pacull F. [2014] Download
  2. Bartosinski Roman, Daněk Martin, Kafka Leoš, Kohout Lukáš, Sýkora JaroslavThe Architecture and the Technology Characterization of an FPGA-Based Customizable Application-Specific Vector Coprocessor (ASVP) , Smart Multicore Embedded Systems, p. 45-77 , Eds: Massimo T., Bertels K., Karlsson S., Pacull F. [2014] Download
  3. Daněk Martin, Kafka Leoš, Kohout Lukáš, Sýkora Jaroslav, Bartosinski RomanUTLEON3: Exploring Fine-Grain Multi-Threading in FPGAs, Springer, (New York 2013) Circuits & Systems [2013]
  4. Schier Jan, Kovář BohumilSimple Tool for Semi-automated Evaluation of Yeast Colony Images , Biomedical Engineering Systems and Technologies, 4th International Joint Conference, BIOSTEC 2011, Revised Selected Papers, p. 110-125 , Eds: Fred Ana, Filipe Joaquim, Gamboa Hugo [2013] Download
  5. Gabriel J., Schier Jan, Van Huffel S., Conchon E., Correia C., Fred A., Gamboa H.Biomedical Engineering Systems and Technologies, Springer, (Berlin Heidelberg 2013) Communications in Computer and Information Science vol.357 [2013] Download
  6. Dulík T., Křivka Z., Kadlec Jiří, Bližňák M., Budíková V., Jirák O., Olšarová N., Trbušek J., Vašíček Z.Virtuální laboratoř pro vývoj aplikací s mikroprocesory a FPGA, CERM, (Brno 2011) [2011] Download
  7. Gamrat Ch., Philippe J. M., Jesshope Ch., Shafarenko A., Bisdounis L., Bondi U., Ferrante A., Cabestany J., Hübner M., Pärsinnen J., Kadlec Jiří, Daněk Martin, Tain B., Eisenbach S., Auguin M., Diguet J. P., Lenormand E., Roux J. L.AETHER: Self-Adaptive Networked Entities: Autonomous Computing Elements for Future Pervasive Applications and Technologies , Reconfigurable Computing. From FPGAs to Hardware/Software Codesign, p. 149-184 , Eds: Cardoso Joao, Hübner Michael [2011] Download
  8. Heřmánek AntonínNext generation equalisation algorithms, LAP LAMBERT Academic Publishing GmbH & Co, (Saarbrücken 2010) [2010] Download
  9. Hillerová E., Kadlec JiříCzech Republic, Information Society Technology, ÚTIA AV ČR, (Praha 1999) [1999]

Journal articles

  1. Kadlec Jiří, Sebroňová EvaZhodnocení účasti ČR v projektech priority ICT 7. RP v porovnání se zeměmi EU-12 , Echo, 3 (2014), p. 9-12 [2014] Download
  2. Baxa Monika, Hruška-Plocháň Marian, Juhás Štefan, Vodička Petr, Pavlok Antonín, Juhásová Jana, Miyanohara A., Nejime T., Klíma Jiří, Mačáková Monika, Marsala S., Weiss A., Kubíčková S., Musilová P., Vrtel R., Sontag E. M., Thompson L.M., Schier Jan, Hansíková H., Howland D. S., Cattaneo E., DiFiglia M., Marsala M., Motlík JanA transgenic minipig model of Hungtington´s disease , Journal of Huntington´s Disease vol.2, 1 (2013), p. 47-68 [2013]
  3. Kadlec JiříElektronika pro zvýšení bezpečnosti malých městských automobilů , Automa vol.19, 2 (2013), p. 54-55 [2013] Download
  4. Kadlec Jiří, Nedvědová K.Artemis JU and Eniac JU Projects with Czech Participation , Automa, p. 6-9 [2013] Download
  5. Kadlec JiříCzech Companies Involved in the ARTEMIS Programme , Automa, p. 4-5 [2013] Download
  6. Matulík RadimPoužívání čidel pohybu k automatickému zapínání osvětlení , Elektro vol.23, 11 (2013), p. 30-31 [2013] Download
  7. Kadlec Jiří, Bystřická J.Výsledky třetí výzvy programu společných technologických iniciativ ARTEMIS JU a ENIAC JU , Echo vol.2011, 2 (2011), p. 18-19 [2011] Download
  8. Daněk Martin, Kafka Leoš, Kohout Lukáš, Sýkora JaroslavHardware Support for Fine-Grain Multi-Threading in LEON3 , Carpathian Journal of Electronic and Computer Engineering vol.4, 1 (2011), p. 27-34 [2011]
  9. Tichý Milan, Schier Jan, Gregg D.GSFAP Adaptive Filtering Using Log Arithmetic for Resource-Constrained Embedded Systems , ACM Transactions on Embedded Computing Systems vol.9, 3 (2010), p. 1-31 [2010] Download
  10. Coleman J. N., Softley C. I., Kadlec Jiří, Matoušek R., Tichý Milan, Pohl Zdeněk, Heřmánek Antonín, Benschop N. F.The European Logarithmic Microprocessor , IEEE Transactions on Computers vol.57, 4 (2008), p. 532-546 [2008] Download
  11. Pohl Zdeněk, Tichý Milan, Kadlec JiříImplementation of the Least-Squares Lattice with Order and Forgetting Factor Estimation for FPGA , EURASIP Journal on Advances in Signal Processing vol.2008, 2008 (2008), p. 1-11 [2008] Download
  12. Kadlec Jiří, Vaculíková E.ARTEMIS - šance pro výzkum v oboru vestavných systémů - polemika , Automa vol.13, 10 (2007), p. 13-15 [2007]
  13. Šůcha P., Hanzálek Z., Heřmánek Antonín, Schier JanScheduling of Iterative Algorithms with Matrix Operations for Efficient FPGA Design—Implementation of Finite Interval Constant Modulus Algorithm , Journal of Vlsi Signal Processing Systems for Signal Image and Video Technology vol.46, 1 (2007), p. 35-53 [2007] Download
  14. Daněk Martin, Honzík Petr, Kadlec Jiří, Pohl Zdeněk, Matoušek RudolfPlatforma s částečnou dynamickou rekonfigurací FPGA , Automa vol.12, 5 (2006), p. 40-43 [2006]
  15. Matoušek Rudolf, Daněk Martin, Kubátová H.Perspektivy dynamické rekonfigurace programovatelných polí FPGA , Sdělovací technika vol.54, 4 (2006), p. 3-6 [2006]
  16. Kadlec Jiří, Chappel S.Implementing floating-point DSP , Embedded Magazine vol.2, 3 (2006), p. 12-14 [2006] Download
  17. Kadlec Jiří, Vaculíková E.Podpora projektů informační a komunikační techniky v 7.rámcovém programu EU pro výzkum , Automa vol.13, 5 (2006), p. 82-83 [2006]
  18. Daněk MartinProgramovatelná hradlová pole - FPGA , Automa vol.12, 2 (2006), p. 9-13 [2006]
  19. Kadlec Jiří, Albrecht V.Význam účasti v projektech EU , Echo vol.2, 2 (2005), p. 11-13 [2005]
  20. Honzík PetrProgramování AVR v aplikaci , Praktická elektronika A Radio vol.10, 4 (2005), p. 20 [2005]
  21. Daněk Martin, Honzík Petr, Kadlec Jiří, Matoušek Rudolf, Pohl ZdeněkReconfigurable system on programmable chip platform , ATMEL Applications Journal, p. 9-12 [2005]
  22. Matoušek Rudolf, Daněk Martin, Pohl Zdeněk, Bartosinski Roman, Honzík PetrReconfigurable System-on-a-Chip , Syndicated vol.5, 2 (2005), p. 1-3 [2005]
  23. Kadlec JiříIDEALIST: Jak najít partnery pro projekty IST , Echo, p. 13 [2004]
  24. Mazanec Tomáš, Brothánek M.FPGA implementace LMS a N-LMS algoritmu pro potlačení akustického echa , Akustické listy vol.10, 4 (2004), p. 9-13 [2004]
  25. Honzík PetrElektronická kniha jízd , Elektus -- "Speciál" : ročenka časopisu Praktická elektronika A Radio, p. 34-38 [2004]
  26. Kadlec Jiří, Matoušek Rudolf, Heřmánek Antonín, Líčko Miroslav, Tichý MilanLattice for FPGAs using logarithmic arithmetic , Electronic Engineering vol.74, 906 (2002), p. 53-56 [2002]
  27. Coleman J. N., Chester E. I., Softley C. I., Kadlec JiříArithmetic on the European Logarithmic Microprocessor , IEEE Transactions on Computers vol.49, 7 (2000), p. 702-715 [2000]
  28. Hlavička J., Kadlec JiříVstup do evropské informační společnosti - program IST , Automa vol.6, 7 (2000), p. 105-107 [2000]
  29. Kadlec Jiří, Schier JanAnalysis of a normalized QR filter using Bayesian description of propagated data , International Journal of Adaptive Control and Signal Processing vol.13, 6 (1999), p. 487-505 [1999]
  30. Matulík RadimGIN - zápisník pro nevidomé , Computer World vol.8, 10 (1997), p. 45 [1997]
  31. Kadlec Jiří, Gaston F. M. F., Irwin G. W.A parallel fixed-point predictive controller , International Journal of Adaptive Control and Signal Processing vol.11, 5 (1997), p. 415-430 [1997] Download
  32. Schier JanEstimation of transport delay using parallel recursive modified Gram-Schmidt algorithm , International Journal of Adaptive Control and Signal Processing vol.11, 5 (1997), p. 431-442 [1997] Download
  33. Matulík RadimNotebook for the blind , ERCIM News, p. 19 [1997]
  34. Schier JanInverse updated systolic RLS algorithm with regularized exponential forgetting , Kybernetika vol.32, 3 (1996), p. 209-234 [1996] Download
  35. Kadlec JiříTransputer implementation of block regularized filtering , Kybernetika vol.32, 3 (1996), p. 235-250 [1996]
  36. Kadlec Jiří, Gaston F. M. F., Irwin G. W.The block regularised parameter estimator and its parallelisation , Automatica vol.31, 8 (1995), p. 1125-1136 [1995] Download
  37. Schier JanA systolic algorithm for block-regularized RLS identification , Integration, the VLSI Journal vol.20, p. 85-100 [1995] Download

Other publications

  1. Sýkora JaroslavComposing Data-driven Circuits Using Handshake in the Clock-Synchronous Domain , Proceedings of the 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), p. 211-214, 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), (Karlovy Vary, CZ, 08.04.2013-10.04.2013) [2013] Download
  2. Kubátová H., Hochberger Ch., Daněk Martin, Sick B.Architecture of Computing Systems - ARCS 2013, Springer, (Heidelberg 2013) Lecture Notes in Computer Science vol.7767 , International Conference of the Architecture of Computing Systems - ARCS 2013/ 26./, (Prague, CZ, 19.02.2013-22.02.2013) [2013] Download
  3. Kadlec JiříEDKDSP: Reprogrammable Floating Point Accelerators on KINTEX FPGA with HDMI , 2013 Design, Automation and Test in Europe, DATE 2013 Design, Automation and Test in Europe, (Grenoble, FR, 2013.03.18-2013.03.22) [2013] Download
  4. Kadlec Jiří, Sebroňová E.Setkání zástupců v oblasti ICT v ČR a seznámení s draftem pracovního programu pro oblast ICT v H2020, (Praha, CZ, 13.09.2013-13.09.2013) [2013]
  5. Van Tol M. W., Pohl Zdeněk, Tichý MilanA Framework for Self-adaptive Collaborative Computing on Reconfigurable Platforms , Advances in Parallel Computing, p. 579-586, International Conference on Parallel Computing, (Ghent, BE, 30.08.2011-02.09.2011) [2012] Download
  6. Schier Jan, Correia C., Fred A., Gamboa H.BIOINFORMATICS 2012, Proceedings of the International Conference on Bioinformatics Models, Methods and Algorithms, SciTePress – Science and Technology Publications, (Algarve 2012) , BIOINFORMATICS 2012, International Conference on Bioinformatics Models, Methods and Algorithms, (Vilamoura, Algarve, PT, 01.02.2012-04.02.2012) [2012]
  7. Bartosinski Roman, Daněk Martin, Sýkora Jaroslav, Kohout LukášForeground Detection and Image Segmentation in a Flexible ASVP Platform for FPGAs, ( 2012) [2012]
  8. Kadlec JiříIn-circuit, Run-time Compiler of Finite State Machines for the UTIA EdkDSP Customizable Accelerators , Fourth Friday Workshop on Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools, and Applications, p. 32-33 , Eds: Silvano Cristina, Agosta Giovanni, Cardoso Joao, DATE 2012 - Design Automation and Test in Europe conference and exhibition, (Dresden, DE, 12.03.2012-16.03.2012) [2012] Download
  9. Sýkora Jaroslav, Kohout Lukáš, Bartosinski Roman, Kafka Leoš, Daněk Martin, Honzík P.The Architecture and the Technology Characterization of an FPGA-based Customizable Application-Specific Vector Processor , Proceedings of the 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, p. 62-67 , Eds: Raik, J. , Stopjaková, V. , Jenihhin, M. , Vierhaus, H., T. , Pleskacz, W. , Ubar, R. , 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, (Tallinn, EE, 18.04.2012-20.04.2012) [2012] Download
  10. Schier Jan, Correia C., Fred A., Gamboa H.BIOINFORMATICS 2012, International Conference on Bioinformatics Models, Methods and Algorithms, (Vilamoura, Algarve, PT, 01.02.2012-04.02.2012) [2012]
  11. Schier Jan, Correia C. M. B. A., Fred A. L. N., Gamboa H.BIOINFORMATICS 2012 - Proceedings of the International Conference on Bioinformatics Models, Methods and Algorithms, SciTePress, (Vilamoura, Algarve 2012) , The International Conference on Bioinformatics Models, Methods and Algorithms, (Vilamoura, Algarve, PT, 01.02.2012-04.02.2012) [2012]
  12. Bartosinski Roman, Daněk Martin, Sýkora Jaroslav, Kohout Lukáš, Honzík P.Video Surveillance Application Based on Application Specific Vector Processors , Proceedings of the 2012 Conference on Design & Architectures for Signal & Image Processing, p. 248-255 , Eds: Morawiec Adam, Hinderscheit Jinnie , Conference on Design & Architectures for Signal & Image Processing, (Karlsruhe, DE, 23.10.2012-25.10.2012) [2012] Download
  13. Schier Jan, Kovář Bohumil, Kočárek E.Automated Detection of Interphase and Metaphase Nuclei in the FISH Images , BIOINFORMATICS 2012, Proceedings of the International Conference on Bioinformatics Models, Methods and Algorithms, p. 347-350 , Eds: Schier Jan, Correia Carlos, Fred Ana, Gamboa Hugo, BIOINFORMATICS 2012, International Conference on Bioinformatics Models, Methods and Algorithms, (Vilamoura, Algarve, PT, 01.02.2012-04.02.2012) [2012]
  14. Lohstroh J., Schutz E., Kadlec JiříARTEMIS Brokerage Event Call 2012, (Praha, CZ, 17.01.2012-18.01.2012) [2012] Download
  15. Sýkora Jaroslav, Bartosinski Roman, Kohout Lukáš, Daněk Martin, Honzík P.Reducing Instruction Issue Overheads in Application-Specific Vector Processors , Proceedings of the 15th Euromicro Conference on Digital System Design, DSD 2012, p. 600-607 , Eds: Niar Smail, 15th Euromicro Conference on Digital System Design, (Cesme, TR, 05.09.2012-08.09.2012) [2012] Download
  16. Kuneš Michal, Schier Jan, Kovář BohumilSignal Selection Tool, ÚTIA AV ČR, v.v.i, (Praha 2012) Internal Publication [2012] Download
  17. Bartosinski Roman, Daněk Martin, Sýkora Jaroslav, Kohout Lukáš, Honzík P.Foreground Detection and Image Segmentation in a Flexible ASVP Platform for FPGAs , Proceedings of the 2012 Conference on Design & Architectures for Signal & Image Processing, p. 375-376 , Eds: Morawiec Adam, Hinderscheit Jinnie , Conference on Design & Architectures for Signal & Image Processing, (Karlsruhe, DE, 23.10.2012-25.10.2012) [2012] Download
  18. Kadlec Jiří, Kafka Leoš, Stejskal J.BASIC IO CORE – Funkční vzorek řadiče elektronického potenciometru, ( 2011) [2011]
  19. Sýkora Jaroslav, Kafka Leoš, Daněk Martin, Kohout LukášAnalysis of Execution Efficiency in the Microthreaded Processor UTLEON3 , Architecture of Computing Systems - ARCS 2011, p. 110-121 , Eds: Berekovic Mladen, ARCS 2011. International Conference on Architecture of computing systems /24./, (Camo, IT, 24.02.2011-25.02.2011) [2011]
  20. Kadlec Jiří, Kafka Leoš, Stejskal J.PWM Core - funkční vzorek generátoru pulzně šířkové modulace, ( 2011) [2011]
  21. Kadlec Jiří, Kafka Leoš, Svozil J.AD Core – Funkční vzorek řadiče A/D převodníku se sběrnicí SPI, ( 2011) [2011]
  22. Honzík P., Kadlec JiříDynamic Placement Applications into Self Adaptive Network on FPGA , 2011 IEEE 14th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS 2011), p. 453-456 , Eds: Vierhaus Heinrich T. , Pawlak Adam, Schölzel Mario, Steininger Andreas, Kraemer Rolf, Raik Jaan, 14th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2011), (Cottbus, DE, 13.04.2011-15.04.2011) [2011] Download
  23. Kadlec JiříÚčast ČR ve společných technologických iniciativách ARTEMIS a ENIAC , Hovory s informatiky, p. 95-113 , Eds: Klímová H., Kuželová D., Šíma J., Wiedermann J., Žák S., Hovory s informatiky 2011, (Praha, CZ, 25.10.2011) [2011] Download
  24. Kadlec Jiří, Kafka Leoš, Svozil J.SPI FLASH Core – Funkční vzorek řadiče paměti SPI Serial Flash, ( 2011) [2011]
  25. Kadlec Jiří, Kafka Leoš, Svozil J.DA Core - Funkční vzorek řadiče D/A převodníku se sběrnicí SPI, ( 2011) [2011]
  26. Kadlec Jiří, Kafka Leoš, Svozil J.FC Core - funkční vzorek čítače frekvence, ( 2011) [2011]
  27. Bartosinski RomanThe LD-RLS algorithm with directional forgetting implemented on a vector-like hardware accelerator , ICASSP 2011: IEEE International Conference on Acoustics, Speech, and Signal Processing, p. 1657-1660, ICASSP 2011: IEEE International Conference on Acoustics, Speech, and Signal Processing, (Praha, CZ, 22.05.2011-27.05.2011) [2011] Download
  28. Kadlec Jiří, Kafka Leoš, Svozil J.LCD Core - Funkční vzorek řadiče LCD displeje, ( 2011) [2011]
  29. Kadlec Jiří, Kafka Leoš, Svozil J.FG Core - funkční vzorek generátoru kmitočtu, ( 2011) [2011]
  30. Kadlec Jiří, Bystřická J., Rakušanová K.Český národní informační den společných technologických iniciativ ARTEMIS a ENIAC, (Praha, CZ, 21.03.2011) [2011]
  31. Schier Jan, Kovář BohumilA semi-automatic software tool for batch processing of yeast colony images , Proceedings of the Eighth IASTED International Conference on Signal Processing, Pattern Recognition, and Applications, p. 206-212 , Eds: Zhang J.J., Eighth IASTED International Conference on Signal Processing, Pattern Recognition, and Applications (SPPRA), (Innsbruck, AT, 16.02.2011-18.02.2011) [2011] Download
  32. Pacull F., Bertels K., Daněk Martin, Urlini G.SMECY: Smarti Multi-core Embedded SYstems (Special Session) , Proceedings of 21st Great Lakes Symposium on VLSI Design - GLSVLSI 2011, p. 427-428, 21st Great Lakes Symposium on VLSI Design - GLSVLSI 2011, (Lausanne, CH, 02.05.2011-04.05.2011) [2011] Download
  33. Pohl Zdeněk, Tichý MilanResource Management for the Heterogeneous Arrays of Hardware Accelerators , Proceedings of 21st International Conference on Field Programmable Logic and Applications, p. 486-489, FPL 2011 International Conference on Field Programmable Logic and Applications (21th), (Chania, GR, 05.09.2011-07.09.2011) [2011] Download
  34. Kadlec Jiří, Kafka Leoš, Svozil J.NOR FLASH Core – Funkční vzorek řadiče paměti Intel StrataFlash, ( 2011) [2011]
  35. Schier Jan, Kovář Bohumil, Kočárek E., Kuneš MichalImage Processing for Automated Analysis of the Fluorescence In-Situ Hybridization (FISH) Microscopic Images , Convergence and Hybrid Information Technology, p. 622-633, 5th International Conference, ICHIT 2011, (Daejeon, KR, 22.09.2011-24.09.2011) [2011] Download
  36. Pohl Zdeněk, Kloub JanDSP Library for UTIA BCE platform, ( 2011) [2011]
  37. Mazanec TomášMIMO techniques for xDSL, ÚTIA AV ČR, (Praha 2011) Research Report 2305 [2011] Download
  38. Schier Jan, Kovář BohumilAutomated counting of yeast colonies using the Fast Radial Transform algorithm , BIOSTEC 2011 4th International Joint Conference on Biomedical Engineering Systems and Technologies, p. 22-27 , Eds: Pellegrini Marco, Fred Ana, Filipe Joaquim, Gamboa Hugo, BIOINFORMATICS 2011 International Conference on Bioinformatics Models, Methods and Algorithms, (Řím, IT, 26.01.2011-29.1.2011) [2011] Download
  39. Sýkora Jaroslav, Kafka Leoš, Daněk Martin, Kohout LukášMicrothreading as a Novel Method for Close Coupling of Custom Hardware Accelerators to SVP Processors , 2011 14th Euromicro Conference on Digital System Design Architectures, Methods and Tools DSD 2011, p. 525-532 , Eds: Kitsos Paris, 14th Euromicro Conference on Digital System Design Architectures, Methods and Tools DSD 2011, (Oulu, FI, 31.08.2011-02.09.2011) [2011] Download
  40. Kloub Jan, Mazanec Tomáš, Heřmánek AntonínHeterogeneous Platform for Stream Based Applications on FPGAs , Proceedings of 21st International Conference on Field Programmable Logic and Applications, p. 401-404, FPL 2011 International Conference on Field Programmable Logic and Applications (21th), (Chania, GR, 05.09.2011-07.09.2011) [2011] Download
  41. Kloub Jan, Honzík Petr, Daněk MartinReconfigurable Hardware Objects for Image Processing on FPGAs , Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, p. 121-122, Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, (Vienna, AT, 14.04.2010-16.04.2010) [2010] Download
  42. Daněk Martin, Kafka Leoš, Kohout Lukáš, Sýkora JaroslavInstruction Set Extensions for Multi-Threading in LEON3 , Proceedings of the13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, p. 237-242, DDECS 2010 : 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, (Vídeň, AT, 14.04.2010-16.04.2010) [2010] Download
  43. Heřmánek Antonín, Kuneš Michal, Tichý MilanReducing Power Consumption of an Embedded DSP Platform through the Clock-Gating Technique , Proceedings of the International Conference on Field Programmable Logic and Applications, p. 336-339, 20th International Conference on Field Programmable Logic and Applications, (Milano, IT, 31.08.2010-02.09.2010) [2010] Download
  44. Kloub JanGraphic Computing Element Description, ( 2010) [2010]
  45. Schier Jan, Kovář BohumilYeast Colony Counter, ( 2010) [2010]
  46. Mazanec Tomáš, Heřmánek Antonín, Kamenický JanBlind image deconvolution algorithm on NVIDIA CUDA platform , Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, p. 125-126, The 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, (Vienna, AT, 14.04.2010-16.04.2010) [2010] Download
  47. Kloub Jan, Mazanec Tomáš, Heřmánek Antonín, Tichý MilanDVB-T2 Receiver Prototype: Physical Layer, ( 2009) [2009]
  48. Tichý MilanÚTIA spoluvyvíjí přijímač pro DVB-T2 , Akademický bulletin AV ČR, 10 (2009), p. 15-15 [2009] Download
  49. Schier JanCounting of yeast colonies in Petri dish images, ( 2009) [2009]
  50. Heřmánek Antonín, Mazanec Tomáš, Tichý MilanDVB-T2 Receiver: Physical Layer Simulator, ( 2009) [2009]
  51. Schier JanPreprocessing of images of Petri dishes, ( 2009) [2009]
  52. Pohl Zdeněk, Tichý MilanSelf-adaptive LMS filter, ( 2009) [2009]
  53. Kuneš Michal, Heřmánek Antonín, Tichý MilanReducing Power Measurements of UTIA DSP platform by Cloack-Gating Technique, Report on Experimental Results, ( 2009) [2009]
  54. Tichý Milan, Pohl Zdeněk, Heřmánek AntonínReed-Solomon Coder Simulation, ( 2009) [2009]
  55. Daněk Martin, Kadlec Jiří, Nelson B.Proceedings 19th International Conference on Field Programmable Logic and Applications (FPL), ÚTIA AV ČR, (Praha 2009) , FPL 2009 19th International Conference on Field Programmable Logic and Applications, (Praha, CZ, 31.08.2009-02.09.2009) [2009]
  56. Schier Jan, Kovář BohumilUsing Matlab in quantitative analysis of yeast growth , Technical Computing Prague 2009, p. 1-9, Technical Computing Prague 2009, (Praha, CZ, 19.11.2009) [2009] Download
  57. Kadlec Jiří, Kadlecová MiladaARTEMIS / ENIAC Joint Undertaking - Seminář ke 2. výzvě, (Praha, CZ, 02.03.2009) [2009]
  58. Kafka Leoš, Daněk MartinNástroj pro přípravu emulace časově anotovaného netlistu, ( 2008) [2008]
  59. Stejskal Jaroslav, Svozil Jiří, Kafka Leoš, Kadlec JiříŘadiče periferií pro vývojovou desku Spartan3E Starter Kit, ( 2008) [2008]
  60. Kovář Bohumil, Kloub Jan, Schier Jan, Heřmánek AntonínRapid Prototyping Platform For Reconfigurable Image Processing , Technical computing Prague 2008. 16th annual conference proceedings, p. 62-62, Technical Computing Prague 2008 /16./, (Praha, CZ, 11.11.2008-11.11.2008) [2008] Download
  61. Daněk Martin, Philippe J.-M., Bartosinski Roman, Honzík Petr, Gamrat Ch.Self-Adaptive Networked Entities for Building Pervasive Computing Aschitectures , International Conference on Evolvable Systems: From Biology to Harware, 8th International Conference, ICES 2008, p. 94-105 , Eds: Hornby Gregory S., Sekanina Lukáš, Haddow Pauline C., International Conference on Evolvable Systems: From Biology to Harware, 8th International Conference, ICES 2008, (Praha, CZ, 22.09.2008-24.09.2008) [2008] Download
  62. Svozil Jiří, Stejskal Jaroslav, Kafka Leoš, Kadlec JiříPicoBlaze lekce 4: Aplikace pro výuku asembleru procesoru PicoBlaze, ( 2008) [2008]
  63. Bartosinski RomanKnihovna Proseccor Expert-Simulink, ( 2008) [2008]
  64. Kadlec JiříDesign Flow for Reconfigurable MicroBlaze Accelerators , 4th International Workshop on Reconfigurable Communication Centric System-on-Chips Workshop Proceedings, p. 133-140 , Eds: Moreno Manuel J., Madrenas Jordi, Sassatelli Gilles, Hübner Michael, Zipf Peter, ReCoSoC 2008 4th Reconfigurable Communication-centric Systems-on-Chip workshop, (Barcelona, ES, 09.07.2008-11.07.2008) [2008]
  65. Kafka Leoš, Daněk MartinRETAC demo – emulátor poruch v2.0, ( 2008) [2008]
  66. Kohout LukášArchitektury číslicových systémů využívající princip samoadaptace , Počítačové architektury a diagnostika 2008 Sborník příspěvků, p. 57-62 , Eds: Plíva Zdeněk, Novák Ondřej, Jeníček Jiří, Rozkovec Martin, Počítačové architektury a diagnostika 2008, (Hejnice, CZ, 15.09.2008-17.09.2008) [2008] Download
  67. Kadlec Jiří, Kadlecová MiladaARTEMIS / ENIAC Joint Undertaking Information event, (Praha, CZ, 16.05.2008) [2008]
  68. Kloub Jan, Heřmánek AntonínImplementace ethernetového rozhraní s podporou protokolu UDP, ( 2008) [2008]
  69. Kloub JanArchitektura systému pro dynamicky rekonfigurovatelný komunikační terminál , Počítačové architektury a diagnostika 2008 Sborník příspěvků, p. 51-56 , Eds: Plíva Zdeněk, Novák Ondřej, Jeníček Jiří, Rozkovec Martin, Počítačové architektury a diagnostika 2008, (Hejnice, CZ, 15.09.2008-17.09.2008) [2008] Download
  70. Stejskal JaroslavZpracování akustických signálů pomocí FPGA, ( 2008) [2008]
  71. Matulík RadimFPGA Embedded Audio Output, ( 2008) [2008]
  72. Kafka LeošAnalysis of Applicability of Partial Runtime Reconfiguration in Fault Emulator in Xilinx FPGAs , Proceedings 2008 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, p. 178-181 , Eds: Straube Bernd, Drutarovský Miloš, Renovell Michel, Gramata Peter, Fischerová Mária, IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems. DDECS 2008 /11./, (Bratislava, SK, 16.04.2008-18.04.2008) [2008]
  73. Kadlec Jiří, Kadlecová Milada, Daněk MartinWorkshop on Embedded Systems Education and Training, (Athény, GR, 05.06.2008) [2008]
  74. Pohl Zdeněk, Kadlec Jiří, Tichý MilanAdaptive Noise Canceller Migration Demo, ( 2008) [2008]
  75. Daněk Martin, Kadlec Jiří, Bartosinski Roman, Kohout LukášIncreasing the Level of Abstraction in FPGA-based Designes , International Conference on Field Programmable Logic and Applications, p. 5-10 , Eds: Kebschull Udo, International Conference on Field Programmable Logic and Applications, (Heidelberg, DE, 08.09.2008-10.09.2008) [2008] Download
  76. Kadlec Jiří, Daněk Martin, Kohout LukášProposed architecture of configurable, adaptable SoC , The IET Irish Signals and Systems Conference ISSC 2008, p. 368-373 , Eds: Morgan Fearghal, Glavin Martin, Jones Edward, The Institution of Engineering and Technology Irish Signals and Systems Conference, ISSC 2008, (Galway, IE, 18.06.2008-19.06.2008) [2008]
  77. Heřmánek Antonín, Kuneš MichalAlamouti core v Celoxica HandelC na Xilinx ML402, ( 2008) [2008]
  78. Bartosinski RomanProcessor Expert AutoSAR-Simulink Library, ( 2008) [2008]
  79. Kovář BohumilRIPAC Frontend - Metodologie tvorby bloků v Simulinku, ( 2008) [2008]
  80. Kovář BohumilDetekce významných bodů v integrální hranové mapě, ( 2007) [2007]
  81. Schier Jan, Kovář Bohumil, Zemčík P., Herout A., Zuzaňák J.Configuration System for a DSP/FPGA-Based Embedded Accelerator , Digital Technologies 2007 Book of Abstracts, p. 32-33 , Eds: Jarina Roman, Digital Technologies 2007, (Žilina, SK, 30.11.2007) [2007]
  82. Heřmánek Antonín, Dušek J., Kloub JanDemonstrátor Reed-Solomonova kodéru a dekodéru s ethernetovým rozhraním implentovaný v FPGA, ÚTIA AV ČR, (Praha 2007) [2007]
  83. Kafka LeošA Novel Emulation Technique that Preserves Circuit Structure and Timing , Počítačové architektury a diagnostika 2007 Sborník příspěvků, p. 99-104 , Eds: Vavřička Vlastimil, Počítačové architektury a diagnostika 2007, (Srní, CZ, 17.09.2007-19.09.2007) [2007]
  84. Kloub Jan, Mazanec Tomáš, Heřmánek AntonínHW Platform for Software Defined Radio, ( 2007) [2007]
  85. Kadlec JiříEmbedded Development Environment for a Family of Xilinx FPGA , Regional Conference on Embedded and Ambient Systems Book of Abstracts, p. 16-16 , Eds: Varga Antila K., Kiss Ákos, Marsiske Stefan, Vásárhelyi József, RCEAS 2007 First Regional Conference on Embedded and Ambient Systems, (Budapešť, HU, 22.11.2007-24.11.2007) [2007]
  86. Pohl Zdeněk, Kadlec Jiří, Tichý MilanAdaptive Noise Canceller Demo based on the LS Lattice Filter, ( 2007) [2007]
  87. Kovář Bohumil, Schier JanKompresní algoritmy a jejich implementace, ( 2007) [2007]
  88. Schier Jan, Kovář Bohumil, Zuzaňák J.Configuration System for a DSP/FPGA-Based Embedded Accelerator , Digital Technologies 2007 Proceedings, p. 1-4 , Eds: Jarina Roman, Digital Technologies 2007, (Žilina, SK, 29.11.2007-30.11.2007) [2007]
  89. Pohl ZdeněkKomunikace pro adm-xrc-4sx, ÚTIA AV ČR, (Praha 2007) [2007]
  90. Mazanec Tomáš, Heřmánek AntonínADSL - ekvalizační techniky, ÚTIA, (Praha 2007) Research Report 2184 [2007]
  91. Mazanec TomášSimulator of ADSL Physical Layer , Technical computing Prague 2007. 15th annual conference proceedings, p. 1-10, Technical computing Prague 2007. 15th annual conference, (Praha, CZ, 14.11.2007-14.11.2007) [2007]
  92. Heřmánek Antonín, Dušek J.Reed Solomonův kodér a dekodér pro FPGA, ÚTIA AV ČR, (Praha 2007) [2007]
  93. Pohl ZdeněkDouble Precision System Generator Library, ÚTIA AV ČR, (Praha 2007) [2007]
  94. Bartosinski Roman, Kadlec JiříSimulation of MCU hardware peripherals , Technical Computing Prague 2007, p. 1-7, Technical Computing Prague 2007, (Praha, CZ, 14.11.2007-14.11.2007) [2007]
  95. Kvasnička M., Heřmánek Antonín, Kuneš MichalAkcelerátor výpočetu věrohodnostní funkce pro systémy pasivní radiolokace, ( 2007) [2007]
  96. Kovář Bohumil, Schier Jan, Zemčík P., Herout A., Zuzaňák J.Simulink Model Converter for Embedded Video Accelerator , Technical Computing Prague 2007, p. 79-79, Technical Computing Prague 2007, (Praha, CZ, 14.11.2007-14.11.2007) [2007]
  97. Kadlec JiříPreparation ARTEMIS and the Czech republic: current status and related issues , Regional Conference on Embedded and Ambient Systems Book of Abstracts, p. 15-15 , Eds: Varga Antila K., Kiss Ákos, Marsiske Stefan, Vásárhelyi József, RCEAS 2007 First Regional Conference on Embedded and Ambient Systems, (Budapešť, HU, 22.11.2007-24.11.2007) [2007]
  98. Kafka Leoš, Daněk Martin, Novák O.Preservation of Circuit Structure and Timing during Fault Emulation in FPGA , IP 07 IP Based Electronic System Conference & Exhibition Proceedings, p. 493-497 , Eds: Saucier Gabriele, Nguyen Huy-Nam, IP 07 IP Based Electronic System Conference & Exhibition, (Grenoble, FR, 05.12.2007-06.12.2007) [2007]
  99. Kafka Leoš, Bartosinski Roman, Daněk MartinAccessory Tools for Partial Dynamic Reconfiguration on Xilinx FPGAs, ÚTIA AV ČR, (Praha 2007) [2007]
  100. Pohl Zdeněk, Daněk MartinFlash Formatter, ÚTIA AV ČR, (Praha 2007) [2007]
  101. Kadlec Jiří, Daněk Martin, Schier Jan, Kohout Lukáš, Kafka Leoš, Kloub Jan, Stejskal Jaroslav, Svozil JiříIdentifikace limitací dosavadních technologií v kontextu projektu VLAM, ÚTIA AV ČR, (Praha 2007) Research Report 2183 [2007]
  102. Pohl Zdeněk, Tichý MilanRLS Lattice Algorithm with Order Probability Evaluation as an Accelerator , Proceedings 2007 International Conference on Field Programmable Logic and Applications (FPL), p. 774-777 , Eds: Bertels Koen, Najjar Walid, Genderen Arjan, Vassiliadis Stamatis, International Conference on Field Programmable Logic and Applications. FPL 2007, (Amsterdam, NL, 27.08.2007-29.08.2007) [2007]
  103. Bartosinski Roman, Hanzálek Z., Stružka P., Waszniowski L.Integrated Environment for Embedded Control Systems Design , Proceedings of the 21st IEEE International Parallel & Distributed Processing Symposium, p. 1-8, 21st IEEE International Parallel & Distributed Processing Symposium, (Long Beach, US, 26.03.2007-30.03.2007) [2007]
  104. Kloub Jan, Heřmánek AntonínAkcelerátor pro výpočet odezvy ADSL vedení, ( 2007) [2007]
  105. Kovář Bohumil, Schier JanKompresní algoritmy a jejich implementace, ÚTIA AV ČR, (Praha 2007) Research Report 2191 [2007]
  106. Mazanec Tomáš, Heřmánek AntonínWebová aplikace pro simulaci ADSL přenosu, ( 2007) [2007]
  107. Kafka LeošDevelopment Kit for Xilinx PicoBlaze, ÚTIA AV ČR, (Praha 2007) [2007] Download
  108. Mazanec Tomáš, Heřmánek AntonínSimulace ADSL downstream přenosu Webová aplikace, ÚTIA AV ČR, (Praha 2007) [2007]
  109. Kohout LukášČástečná dynamická rekonfigurace na FPGA obvodech firmy XILINX, ÚTIA AV ČR, (Praha 2007) [2007]
  110. Pohl ZdeněkKomunikace pro adm-xrc-4sx pomocí ZBIT pamětí, ÚTIA AV ČR, (Praha 2007) [2007]
  111. Kovář BohumilDetekce významných bodů v integrální hranové mapě, ÚTIA AV ČR, (Praha 2007) Research Report 2186 [2007]
  112. Kloub Jan, Heřmánek AntonínAkcelerátor pro dekódování konvolučního a Reed-Solomonova zabezpečovacího kódu , Technical computing Prague 2007. 15th annual conference proceedings, p. 74-74, Technical computing Prague 2007. 15th annual conference, (Praha, CZ, 14.11.2007-14.11.2007) [2007]
  113. Kohout LukášBluetooth modul WT12, ÚTIA AV ČR, (Praha 2007) [2007]
  114. Stejskal Jaroslav, Kafka Leoš, Kadlec JiříPicoBlaze lekce 2: generování VHDL a implementace systému s procesorem PicoBlaze do FPGA v prostředí Xilinx ISE, ÚTIA AV ČR, (Praha 2007) [2007]
  115. Svozil Jiří, Kafka Leoš, Kadlec JiříPicoBlaze lekce 1: assembler, C překladač a simulační prostředí, ÚTIA AV ČR, (Praha 2007) [2007]
  116. Svozil Jiří, Stejskal Jaroslav, Kafka Leoš, Kadlec JiříPicoBlaze lekce 3: sériová komunikace RS232 a testování IP jader pomocí procesoru PicoBlaze, ÚTIA AV ČR, (Praha 2007) [2007]
  117. Stružka P., Waszniowski L., Bartosinski Roman, Bysterský T.Design of Control Application Using Processor Expert Blockset , Technical Computing Prague 2007, p. 1-8, Technical Computing Prague 2007, (Praha, CZ, 14.11.2007-14.11.2007) [2007]
  118. Mazanec Tomáš, Heřmánek AntonínSimulace ekvalizérů TEQ pro ADSL toolbox: výsledky experimentů, ÚTIA AV ČR, (Praha 2007) Research Report 2194 [2007]
  119. Pohl ZdeněkVýstup z Celoxica DK jako BlackBox komponenta Systém Generátoru, ÚTIA AV ČR, (Praha 2007) [2007]
  120. Mazanec Tomáš, Heřmánek AntonínMatlab ADSL Toolbox ver. 11, ( 2007) [2007]
  121. Bartosinski Roman, Daněk Martin, Honzík Petr, Kadlec JiříModelling Self-Adaptive Networked Entities in Matlab/Simulink , Technical Computing Prague 2007, p. 1-8, Technical Computing Prague 2007, (Praha, CZ, 14.11.2007-14.11.2007) [2007]
  122. Kvasnička M., Heřmánek Antonín, Kuneš MichalImplementace akcelerátoru pro výpočet pro výpočet věrohodnostní funkce, ÚTIA AV ČR, (Praha 2007) [2007]
  123. Kafka Leoš, Daněk MartinDevelopment Kit for PicoBlaze Processor in FITkit Board, ÚTIA AV ČR, (Praha 2007) [2007]
  124. Kafka Leoš, Daněk Martin, Novák O.A Novel Emulation Technique that Preserves Circuit Structure and Timing , International Symposium on System-on-Chip 2007 Proceedings, p. 15-18 , Eds: Nurmi J., Takala J., Vainio O., International Symposium on System-on-Chip 2007 /9./, (Tampere, FI, 20.11.2007-21.11.2007) [2007]
  125. Kadlec Jiří, Bartosinski Roman, Daněk MartinAccelerating MicroBlaze Floating Point Operations , Proceedings 2007 International Conference on Field Programmable Logic and Applications (FPL), p. 621-624 , Eds: Bertels Koen, Najjar Walid, Genderen Arjan, Vassiliadis Stamatis, International Conference on Field Programmable Logic and Applications. FPL 2007, (Amsterdam, NL, 27.08.2007-29.08.2007) [2007]
  126. Mazanec Tomáš, Heřmánek AntonínSimulátor fyzické vrstvy ADSL modemu, ÚTIA AV ČR, (Praha 2007) [2007]
  127. Tichý MilanReview and Classification of Adaptive Filtering Algorithms for the LNS Arithmetic, ÚTIA AV ČR, (Praha 2006) Research Report 2162 [2006]
  128. Kadlec Jiří, Kadlecová MiladaPřechod ústavů Akademie věd na V.V.I . a jeho dopad na běžící projekty 6.RP EU, (Praha, CZ, 14.11.2006) [2006]
  129. Schier Jan, Kovář BohumilA DSP/FPGA-based accelerator for video , Digital Technologies 2006, p. 1-5, Digital Technologies 2006, (Žilina, SK, 01.12.2006) [2006]
  130. Pohl Zdeněk, Kadlec JiříRLS Lattice Demo, ÚTIA AV ČR, (Praha 2006) [2006]
  131. Schier Jan, Kovář BohumilA DSP/FPGA-based accelerator for video processing , Digital Technologies 2006 Book of Abstracts, p. 13-13, Digital Technologies 2006, (Žilina, SK, 01.12.2006) [2006]
  132. Šůcha P., Hanzálek Z., Heřmánek Antonín, Schier JanEfficient FPGA Implementation of Equalizer for Finite Interval Constant Modulus Algorithm , IEEE Symposium on Industrial Embedded Systems - IES 2006, Proceedings of, p. 1-10, IEEE Symposium on Industrial Embedded Systems - IES 2006, (Antibes Juan-Les-Pins, FR, 18.10.2006-20.10.2006) [2006]
  133. Ozer E., Tichý Milan, Gregg D.Automatic customization of embedded applications for enhanced performance and reduced power using optimizing compiler techniques , Proceedings of the 12th Workshop on Compilers for Parallel Computers. CPC 2006, p. 16-27 , Eds: Arenaz M., Doallo R., Fraguela B.B., Workshop on Compilers for Parallel Computers. CPC 2006. /12./, (A Coruňa, ES, 09.01.2006-11.01.2006) [2006]
  134. Tichý MilanFloatin-point Arithmetic Library and the FAL maltlab Toolbox. (program), ÚTIA AV ČR, (Praha 2006) [2006]
  135. Kafka Leoš, Novák O.FPGA-based fault simulator , Proceedings of the 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits adn Systems, p. 274-278 , Eds: Reorda M. S., Novák O., Straube B., DDECS 2006. IEEE Design and Diagnostics of Electronic Circuits and Systems, (Prague, CZ, 18.04.2006-21.04.2006) [2006]
  136. Heřmánek Antonín, Kuneš Michal, Kvasnička M.Using Reconfigurable HW for High Dimensional CAF Computation , Proceeding 2006 International Conference on Field Programmable Logic and Applications, p. 641-644 , Eds: Koch A., Leong P., Boemo E., International Conference on Field Programmable Logic and Applications. 2006, (Madrid, ES, 28.08.2006-30.08.2006) [2006]
  137. Tichý Milan, Nisbet A., Gregg D.GSFAP adaptive filtering using log arithmetic for rescouse-constrained embedded systems , FPGA 2006. Fourteenth ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, p. 236-236 , Eds: Wilton S., DeHon A., FPGA 2006. ACM/SIGDA International Symposium on Field-Programmable Gate Arrays /14./, (Monterey, US, 22.02.2006-24.02.2006) [2006]
  138. Kadlec Jiří, Daněk MartinDesign and verification methodology for reconfigurable designs in Atmel FPSLIC , Proceedings of the 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits adn Systems, p. 79-80 , Eds: Reorda M. S., Novák O., Straube B., DDECS 2006. IEEE Design and Diagnostics of Electronic Circuits and Systems, (Prague, CZ, 18.04.2006-21.04.2006) [2006]
  139. Bartosinski Roman, Hanzálek Z., Waszniowski L., Stružka P.Processor Expert Enhances Matlab Simulink Facilities for Embedded Software Rapid Development , Emerging Technologies and Factory Automation 2006, p. 1-4, IEEE Conference on Emerging Technologies and Factory Automation 2006, (Prague, CZ, 20.09.2006-22.09.2006) [2006]
  140. Mazanec TomášAdvanced Algorithms for Equalization on ADSL Channel , Technical computing Prague 2006. 14th annual conference proceedings, p. 68-75 , Eds: Procházka A., Technical computing Prague 2006 /14./, (Prague, CZ, 26.10.2006) [2006]
  141. Kadlec Jiří, Kadlecová MiladaRobotics in IST FP7, (Praha, CZ, 07.11.2006) [2006]
  142. Heřmánek Antonín, Kuneš Michal, Kvasnička M.Comuputation of Long Time Cross Ambiguity function using reconfigurable HW , Proceedings of the 6th IEEE International Symposium on Signal Processing and Information Technology, p. 1-5, IEEE International Symposium on Signal Processing and Information Technology. ISSPIT'06 /6./, (Vancouver, CA, 27.08.2006-30.08.2006) [2006]
  143. Tichý Milan, Schier Jan, Gregg D.FPGA Implementation of Adaptive Filters based on GSFAP using Log Arithmetic , Proceedings of The 2006 IEEE Workshop on Signal Processing Systems Design and Implementation, p. 342-347 , Eds: Badawy W., Boumaiza S., IEEE Workshop on Signal Processing Systems Design and Implementation. 2006, (Banff, CA, 02.10.2006-04.10.2006) [2006]
  144. Tichý Milan, Schier Jan, Gregg D.Efficient Floating-Point Implementation of High-Order (N)LMS Adaptive Filters in FPGA , Reconfigurable Computing: Architecures and Applications. Proceedings of the Second International Workshop ARC, p. 311-316 , Eds: Bertels K., Cardoso J. M. P., Vassiliadis S., The Second International Workshop on Reconfigurable Computing ARC 2006, (Delft, NL, 01.03.2006-03.03.2006) [2006]
  145. Kovář Bohumil, Schier Jan, Zemčík P., Herout A., Beran V.Simulink as Tool for Prototyping Reconfigurable Image Processing Applications , Technical computing Prague 2006. 14th annual conference proceedings, p. 52-57 , Eds: Procházka A., Technical computing Prague 2006 /14./, (Prague, CZ, 26.10.2006) [2006]
  146. Tichý MilanAdaptive Filtering Algorithms Implementation and Evaluation of their Filtering Properties, ÚTIA AV ČR, (Praha 2006) Research Report 2164 [2006]
  147. Tichý MilanEfficient Floating-point-like Implementation of the (N)LMS and GSFAP Algorithms in FPGA, ÚTIA AV ČR, (Praha 2006) Research Report 2165 [2006]
  148. Bartosinski Roman, Kadlec JiříHardware co-simulation with communication server from MATLAB/Simulink , Technical computing Prague 2006. 14th annual conference proceedings, p. 13-20 , Eds: Procházka A., Technical computing Prague 2006 /14./, (Prague, CZ, 26.10.2006) [2006]
  149. Bartosinski Roman, Daněk Martin, Honzík Petr, Matoušek RudolfDynamic reconfiguration in FPGA-based SoC designs , ACACES 2005. Advanced Computer Architecture and Compilation for Embedded Systems, p. 35-38 , Eds: Bosschere K., HiPEAC Network of Excellence, (Ghent 2005) , ACACES 2005., (L'Aquila, IT, 26.07.2005) [2005]
  150. Heřmánek Antonín, Kvasnička M., Pelant M., Plšek R.Passive coherent location FPGA implementation of the cross ambiguity function , Proceedings of SPIE: Signal Processing Symposium 2005, p. 1-7, Signal Processing Symposium 2005, (Wilga, PL, 03.06.2005-05.06.2005) [2005]
  151. Heřmánek Antonín, Schier JanFPGA implementation of Finite Interval CMA , Proceedings of the first annual IEEE BENELUX/DSP Valley Signal Processing Symposium. SPS-DARTS 2005, p. 97-100, IEEE, (Antverpy 2005) , SPS-DARTS 2005 Signal Processing Symposium /1./, (Antverpy, BE, 19.04.2005-20.04.2005) [2005]
  152. Bartosinski Roman, Daněk Martin, Honzík Petr, Matoušek RudolfDynamic reconfiguration in FPGA-based SoC designs , Proceedings of the 8th IEEE Workshop on Designs and Diagnostics of Electronic Circuits nad Systems, p. 129-136 , Eds: Takách G., Hlawiczka A., Sziraj J., University of West Hungary, (Sopron 2005) , IEEE Design and Diagnostics of Electronic Circuits nad Systems Workshop (DDECS 2005) /8./, (Sopron, HU, 13.04.2005-16.04.2005) [2005]
  153. Kafka LeošAn FPGA-based fault injector for TSC circuits , Počítačové architektury a diagnostika, p. 77-81 , Eds: Lórencz R., Buček J., Zahradnický T., ČVUT FEL, (Praha 2005) , Počítačové architektury a diagnostika 2005. PAD 2005, (Lázně Sedmihorky, CZ, 21.09.2005-23.09.2005) [2005]
  154. Kafka Leoš, Kielbik R., Matoušek Rudolf, Moreno J. M.VPart: An automatic partitioning tool for dynamic reconfiguration. Abstract , FPGA 2005 - ACM/SIGDA Thirteenth International Symposium on Field-Programmable Gate Arrays, p. 263 , Eds: Schmidt H., Wilton S., ACM, (Monterey 2005) , FPGA 2005 /13./, (Monterey, US, 20.02.2005-22.02.2005) [2005]
  155. Kadlec JiříDouble Precision Simulation Package double-dk-rel2. (Program), ÚTIA AV ČR, (Praha 2005) [2005]
  156. Bartosinski Roman, Daněk Martin, Honzík Petr, Matoušek RudolfDynamic reconfiguration in FPGA-based SoC designs. Abstract , FPGA 2005 - ACM/SIGDA Thirteenth ACM International Symposium on Field-Programmable Gate Arrays, p. 274 , Eds: Schmidt H., Wilton S., ACM, (Monterey 2005) , FPGA 2005 /13./, (Monterey, US, 20.02.2005-22.02.2005) [2005]
  157. Kadlec Jiří, Kadlecová MiladaVýměna zkušeností řešitelů evropských projektů po 1. kole auditů 6. RPEU, (Praha, CZ, 03.11.2005) [2005]
  158. Heřmánek Antonín, Kvasnička M.Pasivní koherentní radiolokátor FPGA implementace signálového akcelerátoru , Sborník 3. mezinárodní konference Aktivní a Pasivní radiotechnické systémy, p. 1-9, Aktivní a Pasivní radiotechnické systémy, (Brno, CZ, 04.05.2005-05.05.2005) [2005]
  159. Šůcha P., Heřmánek Antonín, Schier Jan, Hanzálek Z.Optimization of Finite Interval CMA Implementation for FPGA, ÚTIA AV ČR, (Praha 2005) Research Report 2127 [2005]
  160. Zemčík P., Herout A., Beran V., Fučík A., Schier JanReconfigurable image processing architecture , ICGST International Conference on Graphics, Vision and Image Processing. GVIP-05, p. 1-6, International Conference on Graphics, Vision and Image Processing, (Káhira, EG, 19.12.2005-21.12.2005) [2005]
  161. Bartosinski Roman, Stružka P., Waszniowski L.Peert-blockset for processor export and matlab/simuling integration , Technical Computing Prague 2005 : 13th Annual Conference Proceedings, p. 1-8 , Eds: Moler C., Procházka A., Walden B., MATLAB 05. Technical Computing Prague 2005, (Praha, CZ, 15.11.2005) [2005]
  162. Heřmánek Antonín, Schier Jan, Šůcha P., Hanzálek Z.Optimization of finite interval CMA implementation for FPGA , Proceedings of the IEEE Workshop on Signal Processing Systems. SiPS 2005, p. 1-6, SiPS 2005. IEEE Workshop on Signal Processing Systems, (Athens, GR, 02.11.2005-04.11.2005) [2005]
  163. Daněk Martin, Heřmánek Antonín, Honzík Petr, Kadlec Jiří, Matoušek Rudolf, Pohl ZdeněkGIN - notetaker for blind people: An example of using dynamic reconfiguration of FPGAs , ACACES 2005. Advanced Computer Architecture and Compilation for Embedded Systems, p. 15-18 , Eds: Bosschere K., HiPEAC Network of Excellence, (Ghent 2005) , ACACES 2005., (L'Aquila, IT, 26.07.2005) [2005]
  164. Kafka Leoš, Matoušek RudolfDesign Retiming in HDL , Proceedings of Workshop 2005, p. 258-259 , Eds: Říha B., ČVUT, (Praha 2005) , Annual University-Wide Seminar. WORKSHOP 2005 /13./, (Praha, CZ, 21.03.2005-25.03.2005) [2005]
  165. Schier Jan, Kovář Bohumil, Zemčík P., Herout A., Beran V.Reconfigurable image processing architecture with simulink prototyping support , Technical Computing Prague 2005. 13th Annual Conference Proceeding, p. 1-4 , Eds: Moler C., Procházka A., Walden B., MATLAB 05. Annual Conference of Technical Computing Prague 2005 /13./, (Praha, CZ, 15.11.2005) [2005]
  166. Mazanec Tomáš, Heřmánek Antonín, Matoušek RudolfModel of the transmission system of the reconnaissance system Orpheus , Technical Computing Prague 2005 : 13th Annual Conference Proceedings, p. 1-4 , Eds: Moler C., Procházka A., Walden B., MATLAB 05. Technical Computing 2005 /13./, (Praha, CZ, 15.11.2005) [2005]
  167. Kadlec JiříScalable Floating Point Simulation Package float-dk-rel2. (Program), ÚTIA AV ČR, (Praha 2005) [2005]
  168. Kadlec Jiří, Gook R.Floating point controller as a picoblaze network on a single spartan 3 FPGA , MAPLD 2005 International Conference Proceeding, p. 1-11 , Eds: Katz R. B., MAPLD 2005 International Conference, (Washington, US, 07.09.2005-09.09.2005) [2005]
  169. Kadlec JiříReconfigurable floating point co-processor for atmel FPSLIC , MAPLD 2005 International Conference Proceedings, p. 1-12 , Eds: Katz R. B., MAPLD 2005 International Conference Proceedings, (Washington, US, 07.09.2005-09.09.2005) [2005]
  170. Nasi K., Daněk Martin, Karoubalis T., Pohl ZdeněkFigaro: An automatic tool flow for designs with dynamic reconfiguration. Abstract , FPGA 2005 - ACM/SIGDA Thirteenth ACM International Symposium on Field-Programmable Gate Arrays, p. 262 , Eds: Schmidt H., Wilton S., ACM, (Monterey 2005) , FPGA 2005 /13./, (Monterey, US, 20.02.2005-22.02.2005) [2005]
  171. Honzík PetrRozbor a implementace dynamické rekonfigurace pro obvody FPGA , Počítačové architektury a diagnostika, p. 55-60 , Eds: Lórencz R., Buček J., Zahradnický T., ČVUT FEL, (Praha 2005) , Počítačové architektury a diagnostika 2005. PAD 2005, (Lázně Sedmihorky, CZ, 21.09.2005-23.09.2005) [2005]
  172. Kafka Leoš, Daněk MartinRETAC Application Notes 2005, ÚTIA AV ČR, (Praha 2005) [2005]
  173. Pohl Zdeněk, Kadlec Jiří, Šůcha P., Hanzálek Z.Performance tuning of interative algorithms in signal processing , Proseedings of the 2005 International Conference on Field Programmable Logic and Applications. FPL 2005, p. 699-702 , Eds: Rissa T., Wilton S., Leong P., FPL 2005. International Conference on Field Programmable Logic and Applications, (Tampere, FI, 24.08.2005-26.08.2005) [2005]
  174. Daněk Martin, Pohl Zdeněk, Nasi K., Karoubalis T.Figaro - an automatic tool flow for designs with dynamic reconfiguration , Proceedings of the 2005 International Conference on Field Programmable Logic and Applications. FPL 2005, p. 590-593 , Eds: Rissa T., Wilton S., Leong P., FPL 2005. International Conference on Field Programmable Logic and Applications, (Tampere, FI, 22.08.2006-26.08.2005) [2005]
  175. Žalud L., Matoušek RudolfARGOS-ORPHEUS system for remote exploration of hazardous environment , Proseedings of the 7th WSEAS International Conference on Automatic Control Modelling and Simulation, p. 10-15 , Eds: Srovnal V., Mastorakis N., Automatic Control Modelling and Simulation. ACMOS 05 /7./, (Praha, CZ, 13.03.2005-15.03.2005) [2005]
  176. Kafka Leoš, Kubalík P., Kubátová H., Novák O.Fault classification for self-checking circuits implemented in FPGA , Proceedings of the 8th IEEE Workshop on Design and Diagnostics of Electronics Circuits and Systems, p. 228-231 , Eds: Takách G., Hlawiczka A., Sziray J., University of West Hungary, (Sopron 2005) , IEEE Design and Diagnostics of Electronics Circuits and Systems Workshop /8./, (Sopron, HU, 13.04.2005-16.04.2005) [2005]
  177. Daněk Martin, Matoušek RudolfOverlay Controller for Atmel FPSLIC, ÚTIA AV ČR, (Praha 2004) Research Report 2113 [2004]
  178. Heřmánek Antonín, Schier Jan, Regalia P.Architecture design for FPGA implementation of finite interval CMA , Proceedings of the 12th European Signal Processing Conference, p. 1-4 , Eds: Hlawatsch F., Matz G., Rupp M., EUSIPCO 2004 /12./, (Vienna, AT, 06.09.2004-10.09.2004) [2004]
  179. Daněk Martin, Honzík Petr, Kadlec Jiří, Matoušek Rudolf, Pohl ZdeněkReconfigurable system-on-a-programmable-chip platform , Proceedings of the 7th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, p. 21-28, IEEE Workshop on DDECS 2004 /7./, (Stará Lesná, SK, 18.04.2004-21.04.2004) [2004]
  180. Kadlec Jiří, Daněk Martin, Honzík PetrReconfigurable Scrolling Demo, ÚTIA AV ČR, (Praha 2004) Research Report 2117 [2004]
  181. Kadlec Jiří, Daněk Martin, Honzík PetrReconfigurable 24-Bit Floating-Point Coprocessor Demo, ÚTIA AV ČR, (Praha 2004) Research Report 2116 [2004]
  182. Honzík PetrAVR core supported dynamic reconfiguration , POSTER 2004. Proceedings of the 8th International Student Conference on Electrical Engineering, p. 1-5 , Eds: Husník L., Lhotská L., International Student Conference on Electrical Engineering. POSTER 2004 /8./, (Praha, CZ, 20.05.2004) [2004]
  183. Matoušek Rudolf, Honzík PetrSDIO Interface for the FPSLIC, ÚTIA AV ČR, (Praha 2004) Research Report 2118 [2004]
  184. Daněk Martin, Matoušek RadomilFLASH Read Controller for Atmel FPSLIC, ÚTIA AV ČR, (Praha 2004) Research Report 2114 [2004]
  185. Honzík PetrGetting Started with AVG-GCC, ÚTIA AV ČR, (Praha 2004) Research Report 2115 [2004]
  186. Matulík RadimGIN z kouzelné lampy míří do kapes , Lidové noviny vol.17, 288 (2004), p. 22 [2004]
  187. Kadlec Jiří, Kadlecová MiladaWorkshop FET. Future and Emerging Technologies in the frame of IST FP6, (Praha, CZ, 14.05.2004) [2004]
  188. Šůcha P., Pohl Zdeněk, Hanzálek ZdeněkScheduling of iterative algorithms on FPGA with pipelined arithmetic unit , Real-Time and Embedded Technology and Applications Symposium, p. 404-412, IEEE Real-Time and Embedded Technology and Applications Symposium 2004 /10./, (Toronto, CA, 25.05.2004-28.05.2004) [2004] Download
  189. Daněk Martin, Kolář J.FPGA modelling for high-performance algorithms. Abstract , FPGA 2004 ACM/SIGDA Twelfth International Symposium on Field-Programmable Gate Arrays, p. 251, FPGA 2004 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays /12./, (Monterey, US, 22.02.2004-24.02.2004) [2004]
  190. Honzík PetrCommunication Library for AVR Microcontrollers, ÚTIA AV ČR, (Praha 2004) Research Report 2110 [2004]
  191. Schier Jan, Heřmánek AntonínFPGA implementation of recursive QR update using LNS arithmetic , Proceedings of the 4th IEEE Benelux Signal Processing Symposium, p. 1-4, SPS 2004 /4./, (Hilvarenbeek, NL, 15.04.2004-16.04.2004) [2004]
  192. Daněk Martin, Matoušek RudolfRandom Access FLASH Controller for Atmel FPSLIC, ÚTIA AV ČR, (Praha 2004) Research Report 2111 [2004]
  193. Schier Jan, Heřmánek AntonínUsing logarithmic arithmetic to implement the Recursive Least Squares (QR) algorithm in FPGA , Field-Programmable Logic and Applications. 14th International Conference FPL 2004. Proceedings, p. 1149-1151, International Conference FPL 2004 /14./, (Antverp, BE, 30.08.2004-01.09.2004) [2004]
  194. Daněk Martin, Matoušek RudolfFLASH Formatter for the FLASH Expansion Board, ÚTIA AV ČR, (Praha 2004) Research Report 2112 [2004]
  195. Pohl Zdeněk, Heřmánek AntonínADPCM IP Cores, ÚTIA AV ČR, (Praha 2004) Research Report 2109 [2004]
  196. Pohl Zdeněk, Heřmánek AntonínADPCM Demo, ÚTIA AV ČR, (Praha 2004) Research Report 2108 [2004]
  197. Líčko Miroslav, Kadlec JiříAn Introduction to the Xilinx System Generator. (Program), ÚTIA AV ČR, (Praha 2003) [2003]
  198. Tichý MilanHSLA Version 3.0.0 Evaluation Package. (Program), ÚTIA AV ČR, (Praha 2003) [2003]
  199. Heřmánková Dana, Kadlecová Milada, Drath P., Hanahoe H.Introduction to the 6th Framework Programme Coordinating EC research projects, ( 2003) , (Praha, CZ, 07.04.2003-08.04.2003) [2003]
  200. Schier JanQR-RLS - Celoxica RC1000 Demo. (Program), ÚTIA AV ČR, (Praha 2003) [2003]
  201. Matoušek Rudolf, Líčko Miroslav, Kadlec JiříEuropean Logarithmic Microprocessor. (Program), ÚTIA AV ČR, (Praha 2003) [2003]
  202. Schier Jan, Kadlec JiříUsing logarithmic arithmetic for FPGA implementation of the Givens rotations , Proceedings of the Sixth Baiona Workshop on Signal Processing in Communications, p. 199-204 , Eds: Mosquera C., Perez-Gonzales F., Universidade de Vigo, (Vigo 2003) , Baiona Workshop on Signal Processing Communications /6./, (Baiona, ES, 08.09.2003-10.09.2003) [2003]
  203. Heřmánková Dana, Rektorová Alice, Trojanowski K., Drath P., Schoefield M., Siemaszko A.Opportunities in the European Union's IST Programme, ( 2003) , (Mragowo, PL, 23.11.2001-24.11.2001) [2003]
  204. Matulík RadimGIN - Pocket Notebook with Synthetic Speech Output for the Blind Users. (Program), ÚTIA AV ČR, (Praha 2003) [2003]
  205. Pohl Zdeněk, Matoušek Rudolf, Kadlec Jiří, Tichý Milan, Líčko M.Lattice adaptive filter implementation for FPGA , FPGA 2003 ACM/SIGDA Eleventh ACM International Symposium on Field-Programmable Gate Arrays, p. 246, ACM, (Monterey 2003) , FPGA 2003, (Monterey, US, 23.02.2003-25.02.2003) [2003]
  206. Líčko Miroslav, Matulík Radim, Matoušek Rudolf, Kadlec JiříPrototyping Board for CAK. (Program), ÚTIA AV ČR, (Praha 2003) [2003]
  207. Matoušek Rudolf, Daněk Martin, Pohl Zdeněk, Kadlec JiříDynamic runtime partial reconfiguration in FPGA , ECMS 2003. 6th International Workshop on Electronics, Control, Measurement and Signals, p. 294-298 , Eds: Nouza J., Drábková J., Technical University, (Liberec 2003) , ECMS 2003 /6./, (Liberec, CZ, 02.06.2003-04.06.2003) [2003]
  208. Matoušek RudolfDynamic reconfiguration of FPGAs: a case study , Počítačové Architektury & Diagnostika PAD 2003, p. 17-23 , Eds: Kotásek Z., Růžička R., Sekanina L., VUT, (Brno 2003) , PAD 2003 Počítačové Architektury & Diagnostika, (Zvíkovské Podhradí, CZ, 24.09.2003-26.09.2003) [2003]
  209. Tichý MilanHSLA Version 4.0.0a Demo. (Program), ÚTIA AV ČR, (Praha 2003) [2003]
  210. Tichý MilanHSLA Package version 3.0.0. Matlab HSLA Toolbox 32- and 19-bit TWIN LNS ALU, ÚTIA AV ČR, (Praha 2003) Research Report 2086 [2003]
  211. Pohl Zdeněk, Kadlec Jiří, Líčko Miroslav, Matoušek Rudolf, Tichý MilanLattice IP Core used in Real-time Lattice Demo on XESS Board. (Program), ÚTIA AV ČR, (Praha 2003) [2003]
  212. Daněk Martin, Muzikář Z.Evolutionary techniques in physical design for FPGAs , ECMS 2003. 6th International Workshop on Electronics, Control, Measurement and Signals, p. 274-278 , Eds: Drábková J., Nouza J., Technical University, (Liberec 2003) , ECMS 2003 /6./, (Liberec, CZ, 02.06.2003-04.06.2003) [2003]
  213. Heřmánek Antonín, Regalia P.Comparison of two recursive constant modulus algorithms , Proceedings of the 4th Electronic Circuits and Systems Conference, p. 159-162 , Eds: Butaš J., Stopjaková V., Slovak University of Technology, (Bratislava 2003) , International Conference on Electronic Circuits and Systems. /4./, (Bratislava, SK, 11.09.2003-12.09.2003) [2003]
  214. Matoušek Rudolf, Pohl Zdeněk, Daněk Martin, Kadlec JiříDynamic reconfiguration of Atmel FPGAs , UK ACM SIGDA 3rd Workshop on Electronic Design Automation, p. 1-4 , Eds: Hettiaratchi S., University of Southampton, (Southampton 2003) , UK ACM SIGDA Workshop on Electronic Design Automation /3./, (Southampton, GB, 11.09.2003-12.09.2003) [2003]
  215. Pohl Zdeněk, Schier Jan, Líčko Miroslav, Heřmánek Antonín, Tichý MilanLogarithmic arithmetic for real data types and support for Matlab/Simulink based rapid-FPGA-prototyping , Proceedings of the International Parallel and Distributed Processing Symposium. IPDPS 2003, p. 1-6 , Eds: Werner B., IEEE Computer Society Press, (Los Alamitos 2003) , IEEE IPDPS 2003, (Nice, FR, 22.04.2003-26.04.2003) [2003]
  216. Daněk MartinIntegrated iterative approach to FPGA placement , Počítačové Architektury & Diagnostika PAD 2003, p. 43-50 , Eds: Kotásek Z., Růžička R., Sekanina L., VUT, (Brno 2003) , PAD 2003 Počítačové Architektury & Diagnostika, (Zvíkovské Podhradí, CZ, 24.09.2003-26.09.2003) [2003]
  217. Matoušek Rudolf, Pohl Zdeněk, Daněk Martin, Kadlec JiříDynamic reconfiguration of FPGAs , Recent Trends in Multimedia Information Processing. Proceedings, p. 288-291 , Eds: Šimák B., Zahradník P., Czech Technical University, (Prague 2003) , International Workshop on Systems, Signals and Image Processing /10./, (Praha, CZ, 10.09.2003-11.09.2003) [2003]
  218. Líčko Miroslav, Schier JanFPGA Prototyping Using Extensions to MATLAB/Simulink , UK ACM SIGDA 3rd Workshop on Electronic Design Automation, p. 1-3 , Eds: Hettiaratchi S., University of Southampton, (Southampton 2003) , UK ACM SIGDA Workshop on Electronic Design Automation /3./, (Southampton, GB, 11.09.2003-12.09.2003) [2003]
  219. Pohl ZdeněkLogarithmic number system and floating-point arithmetics an FPGA , Počítačové Architektury & Diagnostika PAD 2003, p. 9-16 , Eds: Kotásek Z., Růžička R., Sekanina L., VUT, (Brno 2003) , PAD 2003 Počítačové Architektury & Diagnostika, (Zvíkovské Podhradí, CZ, 24.09.2003-26.09.2003) [2003]
  220. Heřmánek Antonín, Pohl Zdeněk, Kadlec JiříFPGA implementation of the adaptive lattice filter , Field-Programmable Logic and Applications. Proceedings of the 13th International Conference, p. 1095-1098 , Eds: Cheung P. Y. K., Constantinides G. A., de Sousa J. D., Springer, (Berlin 2003) Lecture Notes in Computer Science. vol.2778 , Field Programmable Logic and Applications /13./, (Lisabon, PT, 01.09.2003-03.09.2003) [2003]
  221. Líčko Miroslav, Schier Jan, Tichý Milan, Kühl M.MATLAB/Simulink based methodology for rapid-FPGA-prototyping , Field-Programmable Logic and Applications. Proceedings of the 13th International Conference, p. 984-987 , Eds: Cheung P. Y. K., Constantinides G. A., de Sousa J. T., Springer, (Berlin 2003) Lecture Notes in Computer Science. vol.2778 , Field-Programmable Logic and Applications /13./, (Lisabon, PT, 01.09.2003-03.09.2003) [2003]
  222. Pohl Zdeněk, Kadlec Jiří, Tichý MilanRLS Lattice - Celoxica RC200 Demo. (Program), ÚTIA AV ČR, (Praha 2003) [2003]
  223. Albu F., Kadlec Jiří, Coleman N., Fagan A.Pipelined implementations of the A Priory Error-Feedback LSL algorithm using logarithmic arithmetic , Proceedings of the IEEE International Conference on Acoustics, Speech and Signal Processing, p. 2681-2684, IEEE, (Orlando 2002) , ICASSP 2002, (Orlando, US, 13.05.2002-17.05.2002) [2002]
  224. Schier JanUsing the System-C library for bit-true simulations in MATLAB , MATLAB 2002. Sborník příspěvků 10. ročníku konference, p. 497-504, VŠCHT, (Praha 2002) , MATLAB 2002, (Praha, CZ, 07.11.2002) [2002]
  225. Tichý MilanAdaptive Filtering Algorithms and the Logarithmic Number System Arithmetic, ÚTIA AV ČR, (Praha 2002) Research Report 2067 [2002]
  226. Matoušek Rudolf, Líčko Miroslav, Heřmánek Antonín, Softley C.Floating-Point-Like Arithmetic for FPGA , POSTER 2002, p. 2, FEL ČVUT, (Praha 2002) , International Student Conference on Electrical Engineering /6./, (Praha, CZ, 23.05.2002) [2002]
  227. Líčko Miroslav, Schier Jan, Pohl Zdeněk, Kadlec Jiří, Tichý Milan, Matoušek Rudolf, Heřmánek AntonínLogarithmic Arithmetic for Real Data Types and Support for MATLAB/SIMULINK Based Rapid-FPGA-Prototyping, ÚTIA AV ČR, (Praha 2002) Research Report 2069 [2002]
  228. Kadlec Jiří, Tichý Milan, Heřmánek Antonín, Pohl Z., Líčko M.Matlab Toolbox for high-level bit-exact emulation of HandelC VHDL FPGA designs , Design, Automation and Test in Europe DATE˙02, p. 264 , Eds: Sciuto D., Kloos C. D., IEEE, (Los Alamitos 2002) , Design, Automation and Test in Europe DATE˙02, (Paris, FR, 04.03.2002-08.03.2002) [2002]
  229. Heřmánek Antonín, Regalia P.Recursive Finite Interval Constant Modulus Algorithm for blind equalization , MATLAB 2002. Sborník příspěvků 10. ročníku konference, p. 133-141, VŠCHT, (Praha 2002) , MATLAB 2002, (Praha, CZ, 07.11.2002) [2002]
  230. Líčko Miroslav, Tichý Milan, Heřmánek Antonín, Matoušek Rudolf, Pohl ZdeněkPrototyping of DSP algorithms on FPGA , POSTER 2002, p. 2, FEL ČVUT, (Praha 2002) , International Student Conference on Electrical Engineering /6./, (Praha, CZ, 23.05.2002) [2002]
  231. Albu F., Kadlec Jiří, Coleman N., Fagan A.The Gauss-Seidel Fast Affine Projection algorithm , IEEE Workshop on Signal Processing Systems. Proceedings, p. 109-114 , Eds: Parhi K., Shanbhag N., IEEE, (San Diego 2002) , SIPS 2002, (San Diego, US, 16.10.2002-18.10.2002) [2002]
  232. Matoušek R., Pohl Z., Kadlec Jiří, Tichý Milan, Heřmánek AntonínLogarithmic arithmetic core based RLS LATTICE implementation , Design, Automation and Test in Europe DATE 02, p. 271 , Eds: Sciuto D., Kloos C. D., IEEE, (Los Alamitos 2002) , Design, Automation and Test in Europe DATE 02, (Paris, FR, 04.03.2002-08.03.2002) [2002]
  233. Líčko MiroslavFast Adaptive Controllers, ÚTIA AV ČR, (Praha 2002) Research Report 2068 [2002]
  234. Grabowiecki T., Kadlec Jiří, Čerans K., Pihl T., Weber B., Zergoi T.Ideal-ist Conference Information Society Technology in the 6th Framework Programme, ( 2002) , (Varšava, PL, 25.11.2002-26.11.2002) [2002]
  235. Smith B., Edin M., Hillerová E., Kadlecová Milada, Heřmánková Dana, Kadlec Jiříe-2002 e-Work & e-Business Conference, ( 2002) , (Praha, CZ, 16.10.2002-18.10.2002) [2002]
  236. Albu F., Kadlec Jiří, Heřmánek Antonín, Fagan A., Coleman N.Analysis of the LNS implementation of the fast affline projection algorithms , Proceedings of the Irish Signals and Systems Conference 2002. ISSC 2002, p. 251-255 , Eds: Marnane W., Lightbody G., Pesch D., Institute of Technology, (Cork 2002) , Irish Signals and Systems Conference 2002, (Cork, IE, 25.06.2002-26.06.2002) [2002]
  237. Pohl Zdeněk, Líčko M.Utilization of the HSLA toolbox for the FPGA prototyping , MATLAB 2002. Sborník příspěvků 10. ročníku konference, p. 462-468, VŠCHT, (Praha 2002) , MATLAB 2002, (Praha, CZ, 07.11.2002) [2002]
  238. Matoušek Rudolf, Tichý Milan, Pohl Zdeněk, Kadlec Jiří, Softley C.Logarithmic number system and floating-point arithmetics on FPGA , Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream, p. 627-636 , Eds: Glesner M., Zipf P., Renovell M., Springer, (Berlin 2002) Lecture Notes in Computer Science. vol.2438 , International Conference FPL 2002 /12./, (Montpellier, FR, 02.09.2002-04.09.2002) [2002]
  239. Líčko Miroslav, Métais B., Tichý Milan, Matoušek RudolfExtension for Xilinx System Generator - logarithmic arithmetic blockset , MATLAB 2002. Sborník příspěvků 10. ročníku konference, p. 280-284, VŠCHT, (Praha 2002) , MATLAB 2002, (Praha, CZ, 07.11.2002) [2002]
  240. Coleman J. N., Kadlec Jiří, Matoušek Rudolf, Pohl Zdeněk, Heřmánek AntonínThe European Logarithmic Microprocessor - a QRD RLS Applications, ÚTIA AV ČR, (Praha 2001) Research Report 2038 [2001]
  241. Kadlec JiříReview and Classification of RLS Array Algorithms for LNS Arithmetics, ÚTIA AV ČR, (Praha 2001) Research Report 2006 [2001]
  242. Heřmánek Antonín, Kadlec Jiří, Matoušek Rudolf, Líčko Miroslav, Pohl ZdeněkPipelined logarithmic 32bit ALU for Celoxica DK1 , Sborník příspěvků 9.ročníku konference MATLAB 2001, p. 72-80 , Eds: Procházka A., Uhlíř J., VŠCHT, (Praha 2001) , MATLAB 2001 /9./, (Praha, CZ, 11.10.2001) [2001]
  243. Heřmánek Antonín, Kadlec Jiří, Matoušek Rudolf, Líčko Miroslav, Softley Ch.Pipelined Logarithmic 32bit ALU for Celoxica DK1, ÚTIA AV ČR, (Praha 2001) Research Report 2034 [2001]
  244. Schier Jan, Kadlec Jiří, Moonen M.Implementing Advanced Equalization Algorithms using Simulink with Embedded Alpha AXP Coprocessor, ÚTIA AV ČR, (Praha 2001) Research Report 2013 [2001]
  245. Kadlec Jiří, Heřmánek Antonín, Softley Ch., Matoušek Rudolf, Líčko Miroslav32-bit Logarithmic ALU for Handel-C 2.1 and Celoxica DK1, ÚTIA AV ČR, (Praha 2001) Research Report 2037 [2001]
  246. Coleman J. N., Chester E. I., Softley Ch., Kadlec JiříArithmetic on the European Logarithmic Microprocessor, ÚTIA AV ČR, (Praha 2001) Research Report 2012 [2001]
  247. Kadlecová MiladaDetermination of the Problems of Participation in IST for the NAS, ÚTIA AV ČR, (Praha 2001) Research Report 2014 [2001]
  248. Kadlec JiříStructure estimation for systems described by radial basis functions based on normalized QR filtering , Preprints of the 1st IFAC/IEEE Symposium on System Structure and Control, IFAC, (Prague 2001) , IFAC/IEEE Symposium on System Structure and Control /1./, (Prague, CZ, 29.08.2001-31.08.2001) [2001]
  249. Kadlec Jiří, Heřmánková Dana, Rektorová Alice, Drath P., Schoefield M., Martynovicz P.Opportunities in the European Union's IST Programme, ( 2001) , (Praha, CZ, 13.11.2001-14.11.2001) [2001]
  250. Tichý Milan, Kovář BohumilParallel factorised algorithms for mixture estimation , Artificial Neural Nets and Genetic Algorithms. Proceedings, p. 410-413 , Eds: Kůrková V., Neruda R., Kárný M., Steele M. C., Springer, (Wien 2001) , International Conference on Artificial Neural Networks and Genetic Algorithms /5./, (Praha, CZ, 22.04.2001-25.04.2001) [2001]
  251. Matoušek Rudolf, Líčko Miroslav, Heřmánek Antonín, Softley Ch.Floating-Point-Like Arithmetic for FPGA, ÚTIA AV ČR, (Praha 2001) Research Report 2039 [2001]
  252. Albu F., Kadlec Jiří, Matoušek Rudolf, Heřmánek Antonín, Coleman J. N.A Comparison of FPGA Implementation of the A Priori Error-Feedback LSL Algorithm using Logarithmic Arithmetic, ÚTIA AV ČR, (Praha 2001) Research Report 2035 [2001]
  253. Albu F., Kadlec Jiří, Softley Ch., Matoušek Rudolf, Heřmánek AntonínImplementation of Normalized RLS Lattice on Virtex, ÚTIA AV ČR, (Praha 2001) Research Report 2040 [2001]
  254. Kadlec Jiří, Heřmánková Dana, Trojanowski K., Drath P., Schoefield M., Burak R.Managing EC Research Project - Workshop and Brokerage, ( 2001) , (Praha, CZ, 11.12.2001) [2001]
  255. Kadlec Jiří, Kadlecová Milada, Pleger R., Grabowiecki T., Zergoi T., Krekels D.Ideal-ist Workshop European IT Research Programme (IST) Successful Proposal Writing, ( 2001) , (Praha, CZ, 26.09.2001) [2001]
  256. Albu F., Kadlec Jiří, Softley Ch., Matoušek Rudolf, Heřmánek Antonín, Coleman J. N., Fagan A.Implementation of (Normalised) RLS Lattice on Virtex , Field-Programmable Logic and Applications. Proceedings, p. 91-100 , Eds: Brebner G., Woods R., Springer, (Berlin 2001) Lecture Notes in Computer Science. vol.2147 , International Conference FPL 2001, (Belfast, IE, 27.08.2001-29.08.2001) [2001]
  257. Coleman J. N., Kadlec JiříExtended Precision Logarithmic Arithmetic , Signal Systems and Computers 2000, 34th Asilomar Conference on Signal Systems and Computers. Proceedings, p. 124-129, IEEE Signal Processing Society, (Monterey 2001) , Asilomar conference on Signal Systems and Computers /34./, (Monterey, US, 07.11.2000) [2001]
  258. Matoušek Rudolf, Strádal VítLOGAT - Prelimitary Results, ÚTIA AV ČR, (Praha 2001) Research Report 2011 [2001]
  259. Kadlec Jiří, Matoušek Rudolf, Heřmánek Antonín, Líčko Miroslav, Softley Ch.Logarithmic ALU 32-bit for Handel C 2.1 and Celoxica DK1 , Celoxica User Conference. Proceedings, Celoxica, (Abington 2001) , Celoxica User Conference /1./, (Stratford, GB, 02.04.2001-04.04.2001) [2001] Download
  260. Pleger R., Kadlec Jiří, Grabowiecki T., Kadlecová Milada, Krekels D., Heřmánek AntonínIdeal-ist Workshop European IT Research Programme (IST) Successful Proposal Writing, ( 2001) , (Dresden, DE, 17.09.2001) [2001]
  261. Kadlec Jiří, Matoušek Rudolf, Líčko MiroslavFPGA Implementation of Logarithmic Unit Core, ÚTIA AV ČR, (Praha 2001) Research Report 2007 [2001]
  262. Kadlec Jiří, Matoušek Rudolf, Líčko MiroslavFPGA implementation of logarithmic unit core , Embedded Intelligence 2001, p. 547-554, Design & Elektronik, (Nürnberg 2001) , Embedded Intelligence 2001, (Nürnberg, DE, 14.02.2001-16.02.2001) [2001]
  263. Albu F., Kadlec Jiří, Fagan A., Coleman J. N.Implementation of Error-Feedback RLS Lattice on Virtex using logarithmic arithmetic , Advances in Systems Science: Measurement, Circuits and Control. Proceedings, p. 517-521 , Eds: Mastorakis N. E., Pecorelli-Peres L. A., WSES Press, (Rethymno 2001) , WSES Multiconference on Circuits, Systems, Communications & Computers. CSCC 2001 /5./, (Kréta, GR, 08.07.2001-15.07.2001) [2001]
  264. Kadlec Jiří, Albu F., Softley Ch., Matoušek Rudolf, Heřmánek AntonínRLS Lattice for Virtex FPGA using 32-bit and 20-bit Logarithmic Arithmetic, ÚTIA AV ČR, (Praha 2001) Research Report 2036 [2001]
  265. Líčko Miroslav, Matoušek Rudolf, Pohl ZdeněkUtilization of Matlab for the logarithmic processor development , Sborník příspěvků 9.ročníku konference MATLAB 2001, p. 222-225 , Eds: Procházka A., Uhlíř J., VŠCHT, (Praha 2001) , MATLAB 2001 /9./, (Praha, CZ, 11.10.2001) [2001]
  266. Kadlec Jiří, Coleman J. N.Extended Precision LNS Arithmetic, ÚTIA AV ČR, (Praha 2001) Research Report 2008 [2001]
  267. Líčko Miroslav, Pohl Zdeněk, Matoušek Rudolf, Heřmánek AntonínTuning and implementation of DSP algorithms on FPGA , Sborník příspěvků 9.ročníku konference MATLAB 2001, p. 226-230 , Eds: Procházka A., Uhlíř J., VŠCHT, (Praha 2001) , MATLAB 2001 /9./, (Praha, CZ, 11.10.2001) [2001]
  268. Heřmánek Antonín, Matoušek Rudolf, Líčko Miroslav, Kadlec JiříFPGA implementation of logarithmic unit , Sborník příspěvků 8. ročníku konference MATLAB 2000, p. 84-90, VŠCHT, (Praha 2000) , MATLAB 2000 /8./, (Praha, CZ, 01.11.2000) [2000]
  269. Ondračka J., Oravec R., Kadlec Jiří, Cocherová E.Simulation of RLS and LMS algorithms for adaptive noise cancellation in MATLAB , Sborník příspěvků 8. ročníku konference MATLAB 2000, p. 301-305, VŠCHT, (Praha 2000) , MATLAB 2000 /8./, (Praha, CZ, 01.11.2000) [2000]
  270. Hlavička J., Kadlec JiříVstup českých institucí do evropské informační společnosti , Česko-slovenská konference RUFIS 2000, p. 27-32, VUT, (Brno 2000) , Česko-slovenská konference RUFIS 2000., (Brno, CZ, 05.09.2000-06.09.2000) [2000]
  271. Hanzálek ZdeněkMATLAB based Petr Net analysis , Sborník příspěvků 8. ročníku konference MATLAB 2000, p. 78-83, VŠCHT, (Praha 2000) , MATLAB 2000 /8./, (Praha, CZ, 01.11.2000) [2000]
  272. Schier Jan, Kadlec Jiří, Moonen M.Implementing advanced equalization algorithms using Simulink with embedded Alpha AXP coprocessor , Fifth IMA International Conference on Mathematics in Signal Processing, p. 11-14, University of Warwick, (Warwick 2000) , Mathematics in Signal Processing /5./, (Warwick, GB, 18.12.2000-20.12.2000) [2000]
  273. Strádal V., Matoušek RudolfLOGAT , Sborník příspěvků 8. ročníku konference MATLAB 2000, p. 384-386, VŠCHT, (Praha 2000) , MATLAB 2000 /8./, (Praha, CZ, 01.11.2000) [2000]
  274. Matoušek RudolfTraffic Toolbox , Sborník příspěvků 8. ročníku konference MATLAB 2000, p. 232-235, VŠCHT, (Praha 2000) , MATLAB 2000 /8./, (Praha, CZ, 01.11.2000) [2000]
  275. Líčko Miroslav, Matoušek Rudolf, Heřmánek AntonínAlpha accelerator for RTW - Windows Target , Sborník příspěvků 8. ročníku konference MATLAB 2000, p. 197-201, VŠCHT, (Praha 2000) , MATLAB 2000 /8./, (Praha, CZ, 01.11.2000) [2000]
  276. Hillerová E., Kadlec JiříInformační den k programu IST, Technologické centrum AV ČR, (Praha 1999) , Seminář k programu IST /5./, (Praha, CZ, 23.09.1999) [1999]
  277. Kadlec Jiří, Barbier A., de Castellane L., Gautier L.-P., Gourguechon S., Leroy S., Paturle A.Generation of Simulink S-functions, ÚTIA AV ČR, (Praha 1999) Research Report 1975 [1999]
  278. Kadlec Jiří, Matoušek Rudolf, Vialatte Christian, Coleman J. N.Port of Pascal FPGA-logarithmic-unit simulator to Simulink/RTW , Sborník příspěvků 7. ročníku konference MATLAB '99, p. 84-90, VŠCHT, (Praha 1999) , MATLAB '99 /7./, (Praha, CZ, 03.11.1999) [1999]
  279. Vialatte Christian, Kadlec JiříRTW support for parallel 64-bit Alpha AXP-based platforms , Sborník příspěvků 7. ročníku konference MATLAB '99, p. 238-244, VŠCHT, (Praha 1999) , MATLAB '99 /7./, (Praha, CZ, 03.11.1999) [1999]
  280. Hillerová E., Kadlec JiříKonference k zahájení 5. rámcového programu Evropské unie, MŠMT, (Praha 1999) , Konference 5. rámcového programu Evropské unie /5./, (Praha, CZ, 05.02.1999) [1999]
  281. Tesař Ludvík, Berec Luděk, Dolanc G., Szederkényi G., Kadlec JiříA toolbox for model-based fault detection and isolation , European Control Conference. ECC '99, VDI/VDE GMA, (Karlsruhe 1999) , European Control Conference. ECC '99, (Karlsruhe, DE, 31.08.1999-03.09.1999) [1999] Download
  282. Vialatte Christian, Kadlec JiříRTW support for low cost C31 board , Sborník příspěvků 7. ročníku konference MATLAB '99, p. 231-237, VŠCHT, (Praha 1999) , MATLAB '99 /7./, (Praha, CZ, 03.11.1999) [1999]
  283. Schier Jan, Kadlec Jiří, Böhm JosefRobust adaptive controller with fine grain parallelism , Preprints of the IFAC Workshop on Adaptive Systems in Control and Signal Processing, p. 436-441, IFAC, (Glasgow 1998) , Adaptive Systems in Control and Signal Processing, (Glasgow, GB, 26.08.1998-28.08.1998) [1998] Download
  284. Kadlec JiříAcceleration of computation-intensive algorithms on parallel Alpha AXP processors , Preprints of the 3rd European IEEE Workshop on Computer-Intensive Methods in Control and Data Processing, p. 89-98 , Eds: Rojíček J., Valečková M., Kárný M., Warwick K., ÚTIA AV ČR, (Praha 1998) , CMP'98 /3./, (Praha, CZ, 07.09.1998-09.09.1998) [1998] Download
  285. Kadlec Jiří, Schier JanNumerical Analysis of a Normalized QR Filter Using Probability Description of Propagated Data, ÚTIA AV ČR, (Praha 1998) Research Report 1923 [1998]
  286. Kadlec Jiří, Schier JanHSLA 3D Monitor Package, ÚTIA AV ČR, (Praha 1998) Research Report 1925 [1998]
  287. Kadlec Jiří, Schier JanHSLA DSP Package, ÚTIA AV ČR, (Praha 1998) Research Report 1924 [1998]
  288. Swart P. J. F., Schier Jan, van Gemund A. J. C., van der Zwan W. F, Karelse J. P., Reijns G. L., van Genderen P., Ligthart L. P., Steenstra H. T.The COLORADO multistatic FMCW radar system , European Microwave. Proceedings, p. 449-454, Europeam Microwave Association, (London 1998) , European Microwave /28./, (Amsterdam, NL, 06.10.1998-08.10.1998) [1998]
  289. Kadlec Jiří, Schier JanRapid prototyping of adaptive control algorithms on parallel multiprocessors , Signal Processing Symposium, p. 115-118, IEEE, (Leuven 1998) , SPS '98, (Leuven, BE, 26.03.1998-27.03.1998) [1998] Download
  290. Schier JanFast fixed-point algorithm for estimation of the system time lag , Preprints of the 3rd European IEEE Workshop on Computer-Intensive Methods in Control and Data Processing, p. 151-154 , Eds: Rojíček J., Valečková M., Kárný M., Warwick K., ÚTIA AV ČR, (Praha 1998) , CMP'98 /3./, (Praha, CZ, 07.09.1998-09.09.1998) [1998]
  291. Schier Jan, van Gemund A. J. C., Reijns G. L.Real-time signal processing for an obstacle warning radar , Signal Processing Symposium, p. 167-170, IEEE, (Leuven 1998) , SPS '98, (Leuven, BE, 26.03.1998-27.03.1998) [1998]
  292. Schier Jan, van Gemund A. J. C.PTT and OTT Enhancement: Part 2. Final Report, Technical University, (Delft 1998) Research Report 1-68340-44(1998)04 [1998]
  293. Kadlec Jiří, Schier JanResults of the Global Probability Analysis Approach, ÚTIA AV ČR, (Praha 1998) Research Report 1926 [1998]
  294. Kárný Miroslav, Kadlec Jiří, Sutanto E. L.Quasi-Bayes estimation applied to normal mixture , Preprints of the 3rd European IEEE Workshop on Computer-Intensive Methods in Control and Data Processing, p. 77-82 , Eds: Rojíček J., Valečková M., Kárný M., Warwick K., ÚTIA AV ČR, (Praha 1998) , CMP '98 /3./, (Praha, CZ, 07.09.1998-09.09.1998) [1998] Download
  295. Kadlec JiříRapid prototyping and parallel processing under MATLAB 5 , Tagungsband. 3. Zittauer Workshop Magnetlagertechnik, p. 101-104 , Eds: Hampel R., Worlitz F., IPM, (Zittau 1997) Wissenschftliche Berichte. vol.51 , Zittauer Workshop Magnetlagertechnik /3./, (Zittau, DE, 11.09.1997-12.09.1997) [1997] Download
  296. Kadlec JiříPara-Mat parallel processing under MATLAB , Simulationstechnik. Tagungsband, p. 684-687 , Eds: Kuhn A., Wenzel S., Vieweg, (Braunschweig 1997) ASIM vol.11 , Simulationstechnik. /11./, (Dortmund, DE, 11.11.1997-14.11.1997) [1997]
  297. Kadlec Jiří, Vialatte Ch.Rapid prototyping and parallel processing under MATLAB 5 , MATLAB Conference 1997, p. 120-125, Kimhua Technology, (Seoul 1997) , MATLAB Conference '97, (Seoul, KR, 13.10.1997-14.10.1997) [1997]
  298. Kadlec JiříParallel processing on Alphas under MATLAB 5 , SOFSEM '97: Theory and Practice of Informatics, p. 440-448 , Eds: Plášil F., Jeffery K. G., Springer, (Berlin 1997) Lecture Notes in Computer Science. vol.1338 , Seminar on Current Trends in Theory and Practice of Informatics /24./, (Milovy, CZ, 22.11.1997-29.11.1997) [1997]
  299. Schier Jan, Agterkamp H. J., van Gemund A. J. C., Reijns G. L., Lin H. X.Object tracking and tracing for multi-static FM-CW radar - incremental approach , Computer-Intensive Methods in Control and Signal Processing. Preprints of the 2nd European IEEE Workshop CMP'96, p. 151-154 , Eds: Berec L., Rojíček J., Kárný M., Warwick K., ÚTIA AV ČR, (Praha 1996) , European IEEE Workshop CMP'96 /2./, (Prague, CZ, 28.08.1996-30.08.1996) [1996]
  300. Schier Jan, van Gemund A. J. C.PTT and OTT Enhancement - Final Report, University of Technology, (Delft 1996) Research Report 1-68340-44(1996)10 [1996]
  301. Nedoma Petr, Kadlec JiříExtension of MATLAB parallel accelerator , Computer-Intensive Methods in Control and Signal Processing. Preprints of the 2nd European IEEE Workshop CMP'96, p. 155-160 , Eds: Berec L., Rojíček J., Kárný M., Warwick K., ÚTIA AV ČR, (Praha 1996) , European IEEE Workshop CMP'96 /2./, (Prague, CZ, 28.08.1996-30.08.1996) [1996]
  302. McWhirter J. G., Walke R. L., Kadlec JiříNormalised Givens rotations for recursive least squares processing , VLSI Signal Processing, VIII, p. 313-322 , Eds: Nishitani T., Parhi K., IEEE, (New York 1995) , IEEE Workshop on VLSI Signal Processing /8./, (Sakai, JP, 16.10.1995-18.10.1995) [1995]
  303. Kadlec Jiří, Nakhaee N.Alpha-Bridge for MATLAB 4 , Transputer Applications and Systems '95. Proceedings, p. 175-189 , Eds: Cook B. M., Nixon P., IOS Press, (Harrogate 1995) , World Transputer Congress '95, (Harrogate, GB, 04.09.1995-06.09.1995) [1995]
  304. Kadlec Jiří, Gaston F. M. F., Irwin G. W.The block regularised parameter estimator and its parallelisation , Identification and Optimization, Oriented for Use in Adaptive Control. Preprints, p. 107-120 , Eds: Böhm J., Rojíček J., ÚTIA AV ČR, (Praha 1995) , Summer School Course, (Prague, CZ, 17.07.1995-18.07.1995) [1995]
  305. Kadlec Jiří, Gaston F. M. F.Identification with directional parameter tracking for high-performance fixed-point implementations , The Sixth Irish DSP and Control Colloquium, p. 215-222 , Eds: Gaston F., Dodds G., Techman, (Belfast 1995) , IDSPCC '95 /6./, (Belfast, IE, 19.06.1995-20.06.1995) [1995] Download
  306. Schier Jan, Lin H. X., van Gemund A. J. C.Colorado System: Peak Tracking and Tracing Algorithm and its Parallel Implementation, Technische Universiteit, (Delft 1995) Research Report 95-101 [1995]
  307. Kadlec Jiří, Nakhaee N.Alpha Bridge - high performance computing with MATLAB , Industrial Applications of MATLAB and Simulink for the Analysis of Electro- and Hydro- Mechanical Systems. Preprints, p. 11-16, Matlab UG, (Birmingham 1995) , Special Interest Meeting: Industrial Applications /1./, (Birmingham, GB, 20.09.1995) [1995] Download
  308. Kadlec Jiří[Recenze] , Automatica vol.31, 10 (1995), p. 1519-1521 [1995]
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