Institute of Information Theory and Automation

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Bibliography

Antonín Heřmánek

  1. Heřmánek AntonínNext generation equalisation algorithms, LAP LAMBERT Academic Publishing GmbH & Co, (Saarbrücken 2010) [2010] Download

  1. Kloub Jan, Mazanec Tomáš, Heřmánek AntonínHeterogeneous Platform for Stream Based Applications on FPGAs , Proceedings of 21st International Conference on Field Programmable Logic and Applications, p. 401-404, FPL 2011 International Conference on Field Programmable Logic and Applications (21th), (Chania, GR, 05.09.2011-07.09.2011) [2011] Download
  2. Heřmánek Antonín, Kuneš Michal, Tichý MilanReducing Power Consumption of an Embedded DSP Platform through the Clock-Gating Technique , Proceedings of the International Conference on Field Programmable Logic and Applications, p. 336-339, 20th International Conference on Field Programmable Logic and Applications, (Milano, IT, 31.08.2010-02.09.2010) [2010] Download
  3. Mazanec Tomáš, Heřmánek Antonín, Kamenický JanBlind image deconvolution algorithm on NVIDIA CUDA platform , Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, p. 125-126, The 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, (Vienna, AT, 14.04.2010-16.04.2010) [2010] Download
  4. Kovář Bohumil, Kloub Jan, Schier Jan, Heřmánek AntonínRapid Prototyping Platform For Reconfigurable Image Processing , Technical computing Prague 2008. 16th annual conference proceedings, p. 62-62, Technical Computing Prague 2008 /16./, (Praha, CZ, 11.11.2008-11.11.2008) [2008] Download
  5. Kloub Jan, Heřmánek AntonínAkcelerátor pro dekódování konvolučního a Reed-Solomonova zabezpečovacího kódu , Technical computing Prague 2007. 15th annual conference proceedings, p. 74-74, Technical computing Prague 2007. 15th annual conference, (Praha, CZ, 14.11.2007-14.11.2007) [2007]
  6. Mazanec Tomáš, Heřmánek AntonínADSL - ekvalizační techniky, ÚTIA, (Praha 2007) Research Report 2184 [2007]
  7. Šůcha P., Hanzálek Z., Heřmánek Antonín, Schier JanEfficient FPGA Implementation of Equalizer for Finite Interval Constant Modulus Algorithm , IEEE Symposium on Industrial Embedded Systems - IES 2006, Proceedings of, p. 1-10, IEEE Symposium on Industrial Embedded Systems - IES 2006, (Antibes Juan-Les-Pins, FR, 18.10.2006-20.10.2006) [2006]
  8. Heřmánek Antonín, Kuneš Michal, Kvasnička M.Comuputation of Long Time Cross Ambiguity function using reconfigurable HW , Proceedings of the 6th IEEE International Symposium on Signal Processing and Information Technology, p. 1-5, IEEE International Symposium on Signal Processing and Information Technology. ISSPIT'06 /6./, (Vancouver, CA, 27.08.2006-30.08.2006) [2006]
  9. Heřmánek Antonín, Kuneš Michal, Kvasnička M.Using Reconfigurable HW for High Dimensional CAF Computation , Proceeding 2006 International Conference on Field Programmable Logic and Applications, p. 641-644 , Eds: Koch A., Leong P., Boemo E., International Conference on Field Programmable Logic and Applications. 2006, (Madrid, ES, 28.08.2006-30.08.2006) [2006]
  10. Heřmánek Antonín, Schier Jan, Šůcha P., Hanzálek Z.Optimization of finite interval CMA implementation for FPGA , Proceedings of the IEEE Workshop on Signal Processing Systems. SiPS 2005, p. 1-6, SiPS 2005. IEEE Workshop on Signal Processing Systems, (Athens, GR, 02.11.2005-04.11.2005) [2005]
  11. Daněk Martin, Heřmánek Antonín, Honzík Petr, Kadlec Jiří, Matoušek Rudolf, Pohl ZdeněkGIN - notetaker for blind people: An example of using dynamic reconfiguration of FPGAs , ACACES 2005. Advanced Computer Architecture and Compilation for Embedded Systems, p. 15-18 , Eds: Bosschere K., HiPEAC Network of Excellence, (Ghent 2005) , ACACES 2005., (L'Aquila, IT, 26.07.2005) [2005]
  12. Heřmánek Antonín, Schier JanFPGA implementation of Finite Interval CMA , Proceedings of the first annual IEEE BENELUX/DSP Valley Signal Processing Symposium. SPS-DARTS 2005, p. 97-100, IEEE, (Antverpy 2005) , SPS-DARTS 2005 Signal Processing Symposium /1./, (Antverpy, BE, 19.04.2005-20.04.2005) [2005]
  13. Heřmánek Antonín, Kvasnička M., Pelant M., Plšek R.Passive coherent location FPGA implementation of the cross ambiguity function , Proceedings of SPIE: Signal Processing Symposium 2005, p. 1-7, Signal Processing Symposium 2005, (Wilga, PL, 03.06.2005-05.06.2005) [2005]
  14. Heřmánek Antonín, Kvasnička M.Pasivní koherentní radiolokátor FPGA implementace signálového akcelerátoru , Sborník 3. mezinárodní konference Aktivní a Pasivní radiotechnické systémy, p. 1-9, Aktivní a Pasivní radiotechnické systémy, (Brno, CZ, 04.05.2005-05.05.2005) [2005]
  15. Mazanec Tomáš, Heřmánek Antonín, Matoušek RudolfModel of the transmission system of the reconnaissance system Orpheus , Technical Computing Prague 2005 : 13th Annual Conference Proceedings, p. 1-4 , Eds: Moler C., Procházka A., Walden B., MATLAB 05. Technical Computing 2005 /13./, (Praha, CZ, 15.11.2005) [2005]
  16. Pohl Zdeněk, Heřmánek AntonínADPCM IP Cores, ÚTIA AV ČR, (Praha 2004) Research Report 2109 [2004]
  17. Pohl Zdeněk, Heřmánek AntonínADPCM Demo, ÚTIA AV ČR, (Praha 2004) Research Report 2108 [2004]
  18. Schier Jan, Heřmánek AntonínUsing logarithmic arithmetic to implement the Recursive Least Squares (QR) algorithm in FPGA , Field-Programmable Logic and Applications. 14th International Conference FPL 2004. Proceedings, p. 1149-1151, International Conference FPL 2004 /14./, (Antverp, BE, 30.08.2004-01.09.2004) [2004]
  19. Heřmánek Antonín, Schier Jan, Regalia P.Architecture design for FPGA implementation of finite interval CMA , Proceedings of the 12th European Signal Processing Conference, p. 1-4 , Eds: Hlawatsch F., Matz G., Rupp M., EUSIPCO 2004 /12./, (Vienna, AT, 06.09.2004-10.09.2004) [2004]
  20. Schier Jan, Heřmánek AntonínFPGA implementation of recursive QR update using LNS arithmetic , Proceedings of the 4th IEEE Benelux Signal Processing Symposium, p. 1-4, SPS 2004 /4./, (Hilvarenbeek, NL, 15.04.2004-16.04.2004) [2004]
  21. Pohl Zdeněk, Schier Jan, Líčko Miroslav, Heřmánek Antonín, Tichý MilanLogarithmic arithmetic for real data types and support for Matlab/Simulink based rapid-FPGA-prototyping , Proceedings of the International Parallel and Distributed Processing Symposium. IPDPS 2003, p. 1-6 , Eds: Werner B., IEEE Computer Society Press, (Los Alamitos 2003) , IEEE IPDPS 2003, (Nice, FR, 22.04.2003-26.04.2003) [2003]
  22. Heřmánek Antonín, Regalia P.Comparison of two recursive constant modulus algorithms , Proceedings of the 4th Electronic Circuits and Systems Conference, p. 159-162 , Eds: Butaš J., Stopjaková V., Slovak University of Technology, (Bratislava 2003) , International Conference on Electronic Circuits and Systems. /4./, (Bratislava, SK, 11.09.2003-12.09.2003) [2003]
  23. Heřmánek Antonín, Pohl Zdeněk, Kadlec JiříFPGA implementation of the adaptive lattice filter , Field-Programmable Logic and Applications. Proceedings of the 13th International Conference, p. 1095-1098 , Eds: Cheung P. Y. K., Constantinides G. A., de Sousa J. D., Springer, (Berlin 2003) Lecture Notes in Computer Science. vol.2778 , Field Programmable Logic and Applications /13./, (Lisabon, PT, 01.09.2003-03.09.2003) [2003]
  24. Heřmánek Antonín, Regalia P.Recursive Finite Interval Constant Modulus Algorithm for blind equalization , MATLAB 2002. Sborník příspěvků 10. ročníku konference, p. 133-141, VŠCHT, (Praha 2002) , MATLAB 2002, (Praha, CZ, 07.11.2002) [2002]
  25. Albu F., Kadlec Jiří, Heřmánek Antonín, Fagan A., Coleman N.Analysis of the LNS implementation of the fast affline projection algorithms , Proceedings of the Irish Signals and Systems Conference 2002. ISSC 2002, p. 251-255 , Eds: Marnane W., Lightbody G., Pesch D., Institute of Technology, (Cork 2002) , Irish Signals and Systems Conference 2002, (Cork, IE, 25.06.2002-26.06.2002) [2002]
  26. Matoušek Rudolf, Líčko Miroslav, Heřmánek Antonín, Softley C.Floating-Point-Like Arithmetic for FPGA , POSTER 2002, p. 2, FEL ČVUT, (Praha 2002) , International Student Conference on Electrical Engineering /6./, (Praha, CZ, 23.05.2002) [2002]
  27. Líčko Miroslav, Tichý Milan, Heřmánek Antonín, Matoušek Rudolf, Pohl ZdeněkPrototyping of DSP algorithms on FPGA , POSTER 2002, p. 2, FEL ČVUT, (Praha 2002) , International Student Conference on Electrical Engineering /6./, (Praha, CZ, 23.05.2002) [2002]
  28. Kadlec Jiří, Tichý Milan, Heřmánek Antonín, Pohl Z., Líčko M.Matlab Toolbox for high-level bit-exact emulation of HandelC VHDL FPGA designs , Design, Automation and Test in Europe DATE˙02, p. 264 , Eds: Sciuto D., Kloos C. D., IEEE, (Los Alamitos 2002) , Design, Automation and Test in Europe DATE˙02, (Paris, FR, 04.03.2002-08.03.2002) [2002]
  29. Matoušek R., Pohl Z., Kadlec Jiří, Tichý Milan, Heřmánek AntonínLogarithmic arithmetic core based RLS LATTICE implementation , Design, Automation and Test in Europe DATE 02, p. 271 , Eds: Sciuto D., Kloos C. D., IEEE, (Los Alamitos 2002) , Design, Automation and Test in Europe DATE 02, (Paris, FR, 04.03.2002-08.03.2002) [2002]
  30. Matoušek Rudolf, Líčko Miroslav, Heřmánek Antonín, Softley Ch.Floating-Point-Like Arithmetic for FPGA, ÚTIA AV ČR, (Praha 2001) Research Report 2039 [2001]
  31. Líčko Miroslav, Pohl Zdeněk, Matoušek Rudolf, Heřmánek AntonínTuning and implementation of DSP algorithms on FPGA , Sborník příspěvků 9.ročníku konference MATLAB 2001, p. 226-230 , Eds: Procházka A., Uhlíř J., VŠCHT, (Praha 2001) , MATLAB 2001 /9./, (Praha, CZ, 11.10.2001) [2001]
  32. Heřmánek Antonín, Kadlec Jiří, Matoušek Rudolf, Líčko Miroslav, Pohl ZdeněkPipelined logarithmic 32bit ALU for Celoxica DK1 , Sborník příspěvků 9.ročníku konference MATLAB 2001, p. 72-80 , Eds: Procházka A., Uhlíř J., VŠCHT, (Praha 2001) , MATLAB 2001 /9./, (Praha, CZ, 11.10.2001) [2001]
  33. Kadlec Jiří, Matoušek Rudolf, Heřmánek Antonín, Líčko Miroslav, Softley Ch.Logarithmic ALU 32-bit for Handel C 2.1 and Celoxica DK1 , Celoxica User Conference. Proceedings, Celoxica, (Abington 2001) , Celoxica User Conference /1./, (Stratford, GB, 02.04.2001-04.04.2001) [2001] Download
  34. Albu F., Kadlec Jiří, Softley Ch., Matoušek Rudolf, Heřmánek Antonín, Coleman J. N., Fagan A.Implementation of (Normalised) RLS Lattice on Virtex , Field-Programmable Logic and Applications. Proceedings, p. 91-100 , Eds: Brebner G., Woods R., Springer, (Berlin 2001) Lecture Notes in Computer Science. vol.2147 , International Conference FPL 2001, (Belfast, IE, 27.08.2001-29.08.2001) [2001]
  35. Líčko Miroslav, Matoušek Rudolf, Heřmánek AntonínAlpha accelerator for RTW - Windows Target , Sborník příspěvků 8. ročníku konference MATLAB 2000, p. 197-201, VŠCHT, (Praha 2000) , MATLAB 2000 /8./, (Praha, CZ, 01.11.2000) [2000]
  36. Heřmánek Antonín, Matoušek Rudolf, Líčko Miroslav, Kadlec JiříFPGA implementation of logarithmic unit , Sborník příspěvků 8. ročníku konference MATLAB 2000, p. 84-90, VŠCHT, (Praha 2000) , MATLAB 2000 /8./, (Praha, CZ, 01.11.2000) [2000]
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