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Zdeněk Pohl
- Pohl Zdeněk, Tichý Milan, Kadlec Jiří : Implementation of the Least-Squares Lattice with Order and Forgetting Factor Estimation for FPGA , EURASIP Journal on Advances in Signal Processing vol.2008, 2008 (2008), p. 1-11 [2008] Download DOI: 10.1155/2008/394201
- Coleman J. N., Softley C. I., Kadlec Jiří, Matoušek R., Tichý Milan, Pohl Zdeněk, Heřmánek Antonín, Benschop N. F. : The European Logarithmic Microprocessor , IEEE Transactions on Computers vol.57, 4 (2008), p. 532-546 [2008] Download
- Daněk Martin, Honzík Petr, Kadlec Jiří, Pohl Zdeněk, Matoušek Rudolf : Platforma s částečnou dynamickou rekonfigurací FPGA , Automa vol.12, 5 (2006), p. 40-43 [2006]
- Matoušek Rudolf, Daněk Martin, Pohl Zdeněk, Bartosinski Roman, Honzík Petr : Reconfigurable System-on-a-Chip , Syndicated vol.5, 2 (2005), p. 1-3 [2005]
- Daněk Martin, Honzík Petr, Kadlec Jiří, Matoušek Rudolf, Pohl Zdeněk : Reconfigurable system on programmable chip platform , ATMEL Applications Journal, p. 9-12 [2005]
- Pohl Zdeněk, Kohout Lukáš : UTIA Evaluation Board v1.7 v1.8 Beamforming Demo, ( 2019) [2019] Download
- Isakovic H., Grosu R., Ratasich D., Kadlec Jiří, Pohl Zdeněk, Kerrison S. : A Survey of Hardware Technologies for Mixed-Critical Integration Explored in the Project EMC2 , Computer Safety, Reliability, and Security : SAFECOMP 2017 Workshops, ASSURE, DECSoS, SASSUR, TELERISE, and TIPS, p. 127-140 , Eds: Tonetta Stefano, Schoitsch Erwin, Bitsch Friedemann, SAFECOMP 2017 International Conference on Computer Safety, Reliability, and Security, (Trento, IT, 20170912) [2017] Download DOI: 10.1007/978-3-319-66284-8
- Van Tol M. W., Pohl Zdeněk, Tichý Milan : A Framework for Self-adaptive Collaborative Computing on Reconfigurable Platforms , Advances in Parallel Computing, p. 579-586, International Conference on Parallel Computing, (Ghent, BE, 30.08.2011-02.09.2011) [2012] Download DOI: 10.3233/978-1-61499-041-3-579
- Pohl Zdeněk, Tichý Milan : Resource Management for the Heterogeneous Arrays of Hardware Accelerators , Proceedings of 21st International Conference on Field Programmable Logic and Applications, p. 486-489, FPL 2011 International Conference on Field Programmable Logic and Applications (21th), (Chania, GR, 05.09.2011-07.09.2011) [2011] Download
- Pohl Zdeněk, Tichý Milan : RLS Lattice Algorithm with Order Probability Evaluation as an Accelerator , Proceedings 2007 International Conference on Field Programmable Logic and Applications (FPL), p. 774-777 , Eds: Bertels Koen, Najjar Walid, Genderen Arjan, Vassiliadis Stamatis, International Conference on Field Programmable Logic and Applications. FPL 2007, (Amsterdam, NL, 27.08.2007-29.08.2007) [2007]
- Pohl Zdeněk : Výstup z Celoxica DK jako BlackBox komponenta Systém Generátoru, ÚTIA AV ČR, (Praha 2007) [2007]
- Daněk Martin, Heřmánek Antonín, Honzík Petr, Kadlec Jiří, Matoušek Rudolf, Pohl Zdeněk : GIN - notetaker for blind people: An example of using dynamic reconfiguration of FPGAs , ACACES 2005. Advanced Computer Architecture and Compilation for Embedded Systems, p. 15-18 , Eds: Bosschere K., HiPEAC Network of Excellence, (Ghent 2005) , ACACES 2005., (L'Aquila, IT, 26.07.2005) [2005]
- Nasi K., Daněk Martin, Karoubalis T., Pohl Zdeněk : Figaro: An automatic tool flow for designs with dynamic reconfiguration. Abstract , FPGA 2005 - ACM/SIGDA Thirteenth ACM International Symposium on Field-Programmable Gate Arrays, p. 262 , Eds: Schmidt H., Wilton S., ACM, (Monterey 2005) , FPGA 2005 /13./, (Monterey, US, 20.02.2005-22.02.2005) [2005]
- Pohl Zdeněk, Kadlec Jiří, Šůcha P., Hanzálek Z. : Performance tuning of interative algorithms in signal processing , Proseedings of the 2005 International Conference on Field Programmable Logic and Applications. FPL 2005, p. 699-702 , Eds: Rissa T., Wilton S., Leong P., FPL 2005. International Conference on Field Programmable Logic and Applications, (Tampere, FI, 24.08.2005-26.08.2005) [2005]
- Daněk Martin, Pohl Zdeněk, Nasi K., Karoubalis T. : Figaro - an automatic tool flow for designs with dynamic reconfiguration , Proceedings of the 2005 International Conference on Field Programmable Logic and Applications. FPL 2005, p. 590-593 , Eds: Rissa T., Wilton S., Leong P., FPL 2005. International Conference on Field Programmable Logic and Applications, (Tampere, FI, 22.08.2006-26.08.2005) [2005]
- Šůcha P., Pohl Zdeněk, Hanzálek Zdeněk : Scheduling of iterative algorithms on FPGA with pipelined arithmetic unit , Real-Time and Embedded Technology and Applications Symposium, p. 404-412, IEEE Real-Time and Embedded Technology and Applications Symposium 2004 /10./, (Toronto, CA, 25.05.2004-28.05.2004) [2004] Download
- Pohl Zdeněk, Heřmánek Antonín : ADPCM IP Cores, ÚTIA AV ČR, (Praha 2004) Research Report 2109 [2004]
- Daněk Martin, Honzík Petr, Kadlec Jiří, Matoušek Rudolf, Pohl Zdeněk : Reconfigurable system-on-a-programmable-chip platform , Proceedings of the 7th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, p. 21-28, IEEE Workshop on DDECS 2004 /7./, (Stará Lesná, SK, 18.04.2004-21.04.2004) [2004]
- Pohl Zdeněk, Schier Jan, Líčko Miroslav, Heřmánek Antonín, Tichý Milan : Logarithmic arithmetic for real data types and support for Matlab/Simulink based rapid-FPGA-prototyping , Proceedings of the International Parallel and Distributed Processing Symposium. IPDPS 2003, p. 1-6 , Eds: Werner B., IEEE Computer Society Press, (Los Alamitos 2003) , IEEE IPDPS 2003, (Nice, FR, 22.04.2003-26.04.2003) [2003]
- Pohl Zdeněk : Logarithmic number system and floating-point arithmetics an FPGA , Počítačové Architektury & Diagnostika PAD 2003, p. 9-16 , Eds: Kotásek Z., Růžička R., Sekanina L., VUT, (Brno 2003) , PAD 2003 Počítačové Architektury & Diagnostika, (Zvíkovské Podhradí, CZ, 24.09.2003-26.09.2003) [2003]
- Pohl Zdeněk, Kadlec Jiří, Líčko Miroslav, Matoušek Rudolf, Tichý Milan : Lattice IP Core used in Real-time Lattice Demo on XESS Board. (Program), ÚTIA AV ČR, (Praha 2003) [2003]
- Pohl Zdeněk, Kadlec Jiří, Tichý Milan : RLS Lattice - Celoxica RC200 Demo. (Program), ÚTIA AV ČR, (Praha 2003) [2003]
- Matoušek Rudolf, Pohl Zdeněk, Daněk Martin, Kadlec Jiří : Dynamic reconfiguration of Atmel FPGAs , UK ACM SIGDA 3rd Workshop on Electronic Design Automation, p. 1-4 , Eds: Hettiaratchi S., University of Southampton, (Southampton 2003) , UK ACM SIGDA Workshop on Electronic Design Automation /3./, (Southampton, GB, 11.09.2003-12.09.2003) [2003]
- Matoušek Rudolf, Pohl Zdeněk, Daněk Martin, Kadlec Jiří : Dynamic reconfiguration of FPGAs , Recent Trends in Multimedia Information Processing. Proceedings, p. 288-291 , Eds: Šimák B., Zahradník P., Czech Technical University, (Prague 2003) , International Workshop on Systems, Signals and Image Processing /10./, (Praha, CZ, 10.09.2003-11.09.2003) [2003]
- Heřmánek Antonín, Pohl Zdeněk, Kadlec Jiří : FPGA implementation of the adaptive lattice filter , Field-Programmable Logic and Applications. Proceedings of the 13th International Conference, p. 1095-1098 , Eds: Cheung P. Y. K., Constantinides G. A., de Sousa J. D., Springer, (Berlin 2003) Lecture Notes in Computer Science. vol.2778 , Field Programmable Logic and Applications /13./, (Lisabon, PT, 01.09.2003-03.09.2003) [2003]
- Matoušek Rudolf, Daněk Martin, Pohl Zdeněk, Kadlec Jiří : Dynamic runtime partial reconfiguration in FPGA , ECMS 2003. 6th International Workshop on Electronics, Control, Measurement and Signals, p. 294-298 , Eds: Nouza J., Drábková J., Technical University, (Liberec 2003) , ECMS 2003 /6./, (Liberec, CZ, 02.06.2003-04.06.2003) [2003]
- Pohl Zdeněk, Matoušek Rudolf, Kadlec Jiří, Tichý Milan, Líčko M. : Lattice adaptive filter implementation for FPGA , FPGA 2003 ACM/SIGDA Eleventh ACM International Symposium on Field-Programmable Gate Arrays, p. 246, ACM, (Monterey 2003) , FPGA 2003, (Monterey, US, 23.02.2003-25.02.2003) [2003]
- Líčko Miroslav, Schier Jan, Pohl Zdeněk, Kadlec Jiří, Tichý Milan, Matoušek Rudolf, Heřmánek Antonín : Logarithmic Arithmetic for Real Data Types and Support for MATLAB/SIMULINK Based Rapid-FPGA-Prototyping, ÚTIA AV ČR, (Praha 2002) Research Report 2069 [2002]
- Pohl Zdeněk, Líčko M. : Utilization of the HSLA toolbox for the FPGA prototyping , MATLAB 2002. Sborník příspěvků 10. ročníku konference, p. 462-468, VŠCHT, (Praha 2002) , MATLAB 2002, (Praha, CZ, 07.11.2002) [2002]
- Matoušek Rudolf, Tichý Milan, Pohl Zdeněk, Kadlec Jiří, Softley C. : Logarithmic number system and floating-point arithmetics on FPGA , Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream, p. 627-636 , Eds: Glesner M., Zipf P., Renovell M., Springer, (Berlin 2002) Lecture Notes in Computer Science. vol.2438 , International Conference FPL 2002 /12./, (Montpellier, FR, 02.09.2002-04.09.2002) [2002]
- Líčko Miroslav, Tichý Milan, Heřmánek Antonín, Matoušek Rudolf, Pohl Zdeněk : Prototyping of DSP algorithms on FPGA , POSTER 2002, p. 2, FEL ČVUT, (Praha 2002) , International Student Conference on Electrical Engineering /6./, (Praha, CZ, 23.05.2002) [2002]
- Coleman J. N., Kadlec Jiří, Matoušek Rudolf, Pohl Zdeněk, Heřmánek Antonín : The European Logarithmic Microprocessor - a QRD RLS Applications, ÚTIA AV ČR, (Praha 2001) Research Report 2038 [2001]
- Líčko Miroslav, Matoušek Rudolf, Pohl Zdeněk : Utilization of Matlab for the logarithmic processor development , Sborník příspěvků 9.ročníku konference MATLAB 2001, p. 222-225 , Eds: Procházka A., Uhlíř J., VŠCHT, (Praha 2001) , MATLAB 2001 /9./, (Praha, CZ, 11.10.2001) [2001]
- Líčko Miroslav, Pohl Zdeněk, Matoušek Rudolf, Heřmánek Antonín : Tuning and implementation of DSP algorithms on FPGA , Sborník příspěvků 9.ročníku konference MATLAB 2001, p. 226-230 , Eds: Procházka A., Uhlíř J., VŠCHT, (Praha 2001) , MATLAB 2001 /9./, (Praha, CZ, 11.10.2001) [2001]
- Heřmánek Antonín, Kadlec Jiří, Matoušek Rudolf, Líčko Miroslav, Pohl Zdeněk : Pipelined logarithmic 32bit ALU for Celoxica DK1 , Sborník příspěvků 9.ročníku konference MATLAB 2001, p. 72-80 , Eds: Procházka A., Uhlíř J., VŠCHT, (Praha 2001) , MATLAB 2001 /9./, (Praha, CZ, 11.10.2001) [2001]
07.01.2019 - 08:39
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