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Bibliografie
Conference Paper (international conference)
Instruction Set Extensions for Multi-Threading in LEON3
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: Proceedings of the13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, p. 237-242
: DDECS 2010 : 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, (Vídeň, AT, 14.04.2010-16.04.2010)
: CEZ:AV0Z10750506
: FP7-ICT-215216, European Commission, 7E08013, GA MŠk
: multithreading, instruction set extensions, microthreading, LEON3, SPARC, FPGA
(eng): This paper describes instruction set extensions for a variant of multi-threading called micro-threading for the LEON3 SPARCv8 processor. We show an architecture of the developed processor and its key blocks - cache controller, register file, thread scheduler. The processor has been implemented in a Xilinx Virtex2Pro FPGA. The extensions are evaluated in terms of extra resources needed, and the overall performance of the developed processor is evaluated on a simple DSP computation typical for embedded systems.
: JC