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Conference Paper (international conference)

Reducing Instruction Issue Overheads in Application-Specific Vector Processors

Sýkora Jaroslav, Bartosinski Roman, Kohout Lukáš, Daněk Martin, Honzík P.

: Proceedings of the 15th Euromicro Conference on Digital System Design, DSD 2012, p. 600-607 , Eds: Niar Smail

: 15th Euromicro Conference on Digital System Design, (Cesme, TR, 05.09.2012-08.09.2012)

: 7H10001, GA MŠk, Artemis JU 100230, Commission EU

: custom accelerators, vector processing, FPGA, DSP

: http://library.utia.cas.cz/separaty/2012/ZS/sykora-reducing instruction issue overheads in application-specific vector processors.pdf

(eng): The traditional approach to IP core design is to use simulations with test vectors. This is not feasible when dealing with complex function cores such as the Image Segmentation case-study algorithm in this paper. An algorithm developer needs to carry out experiments on large real-world data sets, with fast turn-around times, and in real time to facilitate performance tuning and incremental development. Previously we proposed a methodology called Application-Specific Vector Processor (ASVP). The ASVP approach first constructs a programmable architecture customized for a given application, then employs software techniques to develop firmware that implements the algorithm. In our setting we employ an embedded simple scalar CPU (8-bit PicoBlaze 3) to control a floating-point vector processing unit (VPU) by issuing wide (horizontally encoded) instructions to it. In this work we dramatically reduce the overhead of the wide-instruction issue (in one case by 13x) by implementing a new two-level configuration table.

: JC

07.01.2019 - 08:39