Sýkora Jaroslav, Kohout Lukáš, Bartosinski Roman, Kafka Leoš, Daněk Martin, Honzík P.
:
The Architecture and the Technology Characterization of an FPGA-based Customizable Application-Specific Vector Processor
, Proceedings of the 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems
, Eds: Raik, J. , Stopjaková, V. , Jenihhin, M. , Vierhaus, H., T. , Pleskacz, W. , Ubar, R. , 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems,
(Tallinn, EE, 18.04.2012-20.04.2012) [2012]
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Sýkora Jaroslav, Kafka Leoš, Daněk Martin, Kohout Lukáš
:
Analysis of Execution Efficiency in the Microthreaded Processor UTLEON3
, Architecture of Computing Systems - ARCS 2011
, Eds: Berekovic Mladen, ARCS 2011. International Conference on Architecture of computing systems /24./,
(Camo, IT, 24.02.2011-25.02.2011) [2011]
Daněk Martin, Kafka Leoš, Kohout Lukáš, Sýkora Jaroslav
:
Instruction Set Extensions for Multi-Threading in LEON3
, Proceedings of the13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010 : 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems,
(Vídeň, AT, 14.04.2010-16.04.2010) [2010]
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Kafka Leoš
:
Analysis of Applicability of Partial Runtime Reconfiguration in Fault Emulator in Xilinx FPGAs
, Proceedings 2008 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems
, Eds: Straube Bernd, Drutarovský Miloš, Renovell Michel, Gramata Peter, Fischerová Mária, IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems. DDECS 2008 /11./,
(Bratislava, SK, 16.04.2008-18.04.2008) [2008]
Kafka Leoš, Daněk Martin, Novák O.
:
A Novel Emulation Technique that Preserves Circuit Structure and Timing
, International Symposium on System-on-Chip 2007 Proceedings
, Eds: Nurmi J., Takala J., Vainio O., International Symposium on System-on-Chip 2007 /9./,
(Tampere, FI, 20.11.2007-21.11.2007) [2007]
Kafka Leoš, Daněk Martin, Novák O.
:
Preservation of Circuit Structure and Timing during Fault Emulation in FPGA
, IP 07 IP Based Electronic System Conference & Exhibition Proceedings
, Eds: Saucier Gabriele, Nguyen Huy-Nam, IP 07 IP Based Electronic System Conference & Exhibition,
(Grenoble, FR, 05.12.2007-06.12.2007) [2007]
Kafka Leoš, Novák O.
:
FPGA-based fault simulator
, Proceedings of the 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits adn Systems, p. 274-278
, Eds: Reorda M. S., Novák O., Straube B., DDECS 2006. IEEE Design and Diagnostics of Electronic Circuits and Systems,
(Prague, CZ, 18.04.2006-21.04.2006) [2006]
Kafka Leoš, Kielbik R., Matoušek Rudolf, Moreno J. M.
:
VPart: An automatic partitioning tool for dynamic reconfiguration. Abstract
, FPGA 2005 - ACM/SIGDA Thirteenth International Symposium on Field-Programmable Gate Arrays, p. 263
, Eds: Schmidt H., Wilton S., ACM,
(Monterey 2005)
, FPGA 2005 /13./,
(Monterey, US, 20.02.2005-22.02.2005) [2005]
Kafka Leoš, Kubalík P., Kubátová H., Novák O.
:
Fault classification for self-checking circuits implemented in FPGA
, Proceedings of the 8th IEEE Workshop on Design and Diagnostics of Electronics Circuits and Systems, p. 228-231
, Eds: Takách G., Hlawiczka A., Sziray J., University of West Hungary,
(Sopron 2005)
, IEEE Design and Diagnostics of Electronics Circuits and Systems Workshop /8./,
(Sopron, HU, 13.04.2005-16.04.2005) [2005]
Kafka Leoš
:
An FPGA-based fault injector for TSC circuits
, Počítačové architektury a diagnostika, p. 77-81
, Eds: Lórencz R., Buček J., Zahradnický T., ČVUT FEL,
(Praha 2005)
, Počítačové architektury a diagnostika 2005. PAD 2005,
(Lázně Sedmihorky, CZ, 21.09.2005-23.09.2005) [2005]
Kafka Leoš, Matoušek Rudolf
:
Design Retiming in HDL
, Proceedings of Workshop 2005, p. 258-259
, Eds: Říha B., ČVUT,
(Praha 2005)
, Annual University-Wide Seminar. WORKSHOP 2005 /13./,
(Praha, CZ, 21.03.2005-25.03.2005) [2005]
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