Institute of Information Theory and Automation

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Bibliography

Milan Tichý


    Journal articles

    1. Tichý Milan, Schier Jan, Gregg D.GSFAP Adaptive Filtering Using Log Arithmetic for Resource-Constrained Embedded Systems , ACM Transactions on Embedded Computing Systems vol.9, 3 (2010), p. 1-31 [2010] Download
    2. Pohl Zdeněk, Tichý Milan, Kadlec JiříImplementation of the Least-Squares Lattice with Order and Forgetting Factor Estimation for FPGA , EURASIP Journal on Advances in Signal Processing vol.2008, 2008 (2008), p. 1-11 [2008] Download
    3. Coleman J. N., Softley C. I., Kadlec Jiří, Matoušek R., Tichý Milan, Pohl Zdeněk, Heřmánek Antonín, Benschop N. F.The European Logarithmic Microprocessor , IEEE Transactions on Computers vol.57, 4 (2008), p. 532-546 [2008] Download
    4. Kadlec Jiří, Matoušek Rudolf, Heřmánek Antonín, Líčko Miroslav, Tichý MilanLattice for FPGAs using logarithmic arithmetic , Electronic Engineering vol.74, 906 (2002), p. 53-56 [2002]
    5. Tichý Milan, Zemánek P.Performance and tuning of the UNIX operating system , Journal of Electrical Engineering - Elektrotechnický časopis, p. 74-80 [2001]

    Other publications

    1. Van Tol M. W., Pohl Zdeněk, Tichý MilanA Framework for Self-adaptive Collaborative Computing on Reconfigurable Platforms , Advances in Parallel Computing, p. 579-586, International Conference on Parallel Computing, (Ghent, BE, 30.08.2011-02.09.2011) [2012] Download
    2. Pohl Zdeněk, Tichý MilanResource Management for the Heterogeneous Arrays of Hardware Accelerators , Proceedings of 21st International Conference on Field Programmable Logic and Applications, p. 486-489, FPL 2011 International Conference on Field Programmable Logic and Applications (21th), (Chania, GR, 05.09.2011-07.09.2011) [2011] Download
    3. Heřmánek Antonín, Kuneš Michal, Tichý MilanReducing Power Consumption of an Embedded DSP Platform through the Clock-Gating Technique , Proceedings of the International Conference on Field Programmable Logic and Applications, p. 336-339, 20th International Conference on Field Programmable Logic and Applications, (Milano, IT, 31.08.2010-02.09.2010) [2010] Download
    4. Tichý MilanÚTIA spoluvyvíjí přijímač pro DVB-T2 , Akademický bulletin AV ČR, 10 (2009), p. 15-15 [2009] Download
    5. Kuneš Michal, Heřmánek Antonín, Tichý MilanReducing Power Measurements of UTIA DSP platform by Cloack-Gating Technique, Report on Experimental Results, ( 2009) [2009]
    6. Tichý Milan, Pohl Zdeněk, Heřmánek AntonínReed-Solomon Coder Simulation, ( 2009) [2009]
    7. Kloub Jan, Mazanec Tomáš, Heřmánek Antonín, Tichý MilanDVB-T2 Receiver Prototype: Physical Layer, ( 2009) [2009]
    8. Heřmánek Antonín, Mazanec Tomáš, Tichý MilanDVB-T2 Receiver: Physical Layer Simulator, ( 2009) [2009]
    9. Pohl Zdeněk, Tichý MilanSelf-adaptive LMS filter, ( 2009) [2009]
    10. Pohl Zdeněk, Kadlec Jiří, Tichý MilanAdaptive Noise Canceller Migration Demo, ( 2008) [2008]
    11. Pohl Zdeněk, Kadlec Jiří, Tichý MilanAdaptive Noise Canceller Demo based on the LS Lattice Filter, ( 2007) [2007]
    12. Pohl Zdeněk, Tichý MilanRLS Lattice Algorithm with Order Probability Evaluation as an Accelerator , Proceedings 2007 International Conference on Field Programmable Logic and Applications (FPL), p. 774-777 , Eds: Bertels Koen, Najjar Walid, Genderen Arjan, Vassiliadis Stamatis, International Conference on Field Programmable Logic and Applications. FPL 2007, (Amsterdam, NL, 27.08.2007-29.08.2007) [2007]
    13. Tichý Milan, Schier Jan, Gregg D.FPGA Implementation of Adaptive Filters based on GSFAP using Log Arithmetic , Proceedings of The 2006 IEEE Workshop on Signal Processing Systems Design and Implementation, p. 342-347 , Eds: Badawy W., Boumaiza S., IEEE Workshop on Signal Processing Systems Design and Implementation. 2006, (Banff, CA, 02.10.2006-04.10.2006) [2006]
    14. Tichý Milan, Schier Jan, Gregg D.Efficient Floating-Point Implementation of High-Order (N)LMS Adaptive Filters in FPGA , Reconfigurable Computing: Architecures and Applications. Proceedings of the Second International Workshop ARC, p. 311-316 , Eds: Bertels K., Cardoso J. M. P., Vassiliadis S., The Second International Workshop on Reconfigurable Computing ARC 2006, (Delft, NL, 01.03.2006-03.03.2006) [2006]
    15. Tichý Milan, Nisbet A., Gregg D.GSFAP adaptive filtering using log arithmetic for rescouse-constrained embedded systems , FPGA 2006. Fourteenth ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, p. 236-236 , Eds: Wilton S., DeHon A., FPGA 2006. ACM/SIGDA International Symposium on Field-Programmable Gate Arrays /14./, (Monterey, US, 22.02.2006-24.02.2006) [2006]
    16. Ozer E., Tichý Milan, Gregg D.Automatic customization of embedded applications for enhanced performance and reduced power using optimizing compiler techniques , Proceedings of the 12th Workshop on Compilers for Parallel Computers. CPC 2006, p. 16-27 , Eds: Arenaz M., Doallo R., Fraguela B.B., Workshop on Compilers for Parallel Computers. CPC 2006. /12./, (A Coruňa, ES, 09.01.2006-11.01.2006) [2006]
    17. Tichý MilanFloatin-point Arithmetic Library and the FAL maltlab Toolbox. (program), ÚTIA AV ČR, (Praha 2006) [2006]
    18. Tichý MilanAdaptive Filtering Algorithms Implementation and Evaluation of their Filtering Properties, ÚTIA AV ČR, (Praha 2006) Research Report 2164 [2006]
    19. Tichý MilanReview and Classification of Adaptive Filtering Algorithms for the LNS Arithmetic, ÚTIA AV ČR, (Praha 2006) Research Report 2162 [2006]
    20. Tichý MilanEfficient Floating-point-like Implementation of the (N)LMS and GSFAP Algorithms in FPGA, ÚTIA AV ČR, (Praha 2006) Research Report 2165 [2006]
    21. Tichý MilanHSLA Version 4.0.0a Demo. (Program), ÚTIA AV ČR, (Praha 2003) [2003]
    22. Tichý MilanHSLA Version 3.0.0 Evaluation Package. (Program), ÚTIA AV ČR, (Praha 2003) [2003]
    23. Pohl Zdeněk, Schier Jan, Líčko Miroslav, Heřmánek Antonín, Tichý MilanLogarithmic arithmetic for real data types and support for Matlab/Simulink based rapid-FPGA-prototyping , Proceedings of the International Parallel and Distributed Processing Symposium. IPDPS 2003, p. 1-6 , Eds: Werner B., IEEE Computer Society Press, (Los Alamitos 2003) , IEEE IPDPS 2003, (Nice, FR, 22.04.2003-26.04.2003) [2003]
    24. Pohl Zdeněk, Kadlec Jiří, Líčko Miroslav, Matoušek Rudolf, Tichý MilanLattice IP Core used in Real-time Lattice Demo on XESS Board. (Program), ÚTIA AV ČR, (Praha 2003) [2003]
    25. Pohl Zdeněk, Kadlec Jiří, Tichý MilanRLS Lattice - Celoxica RC200 Demo. (Program), ÚTIA AV ČR, (Praha 2003) [2003]
    26. Líčko Miroslav, Schier Jan, Tichý Milan, Kühl M.MATLAB/Simulink based methodology for rapid-FPGA-prototyping , Field-Programmable Logic and Applications. Proceedings of the 13th International Conference, p. 984-987 , Eds: Cheung P. Y. K., Constantinides G. A., de Sousa J. T., Springer, (Berlin 2003) Lecture Notes in Computer Science. vol.2778 , Field-Programmable Logic and Applications /13./, (Lisabon, PT, 01.09.2003-03.09.2003) [2003]
    27. Tichý MilanHSLA Package version 3.0.0. Matlab HSLA Toolbox 32- and 19-bit TWIN LNS ALU, ÚTIA AV ČR, (Praha 2003) Research Report 2086 [2003]
    28. Pohl Zdeněk, Matoušek Rudolf, Kadlec Jiří, Tichý Milan, Líčko M.Lattice adaptive filter implementation for FPGA , FPGA 2003 ACM/SIGDA Eleventh ACM International Symposium on Field-Programmable Gate Arrays, p. 246, ACM, (Monterey 2003) , FPGA 2003, (Monterey, US, 23.02.2003-25.02.2003) [2003]
    29. Líčko Miroslav, Schier Jan, Pohl Zdeněk, Kadlec Jiří, Tichý Milan, Matoušek Rudolf, Heřmánek AntonínLogarithmic Arithmetic for Real Data Types and Support for MATLAB/SIMULINK Based Rapid-FPGA-Prototyping, ÚTIA AV ČR, (Praha 2002) Research Report 2069 [2002]
    30. Tichý MilanAdaptive Filtering Algorithms and the Logarithmic Number System Arithmetic, ÚTIA AV ČR, (Praha 2002) Research Report 2067 [2002]
    31. Líčko Miroslav, Métais B., Tichý Milan, Matoušek RudolfExtension for Xilinx System Generator - logarithmic arithmetic blockset , MATLAB 2002. Sborník příspěvků 10. ročníku konference, p. 280-284, VŠCHT, (Praha 2002) , MATLAB 2002, (Praha, CZ, 07.11.2002) [2002]
    32. Matoušek Rudolf, Tichý Milan, Pohl Zdeněk, Kadlec Jiří, Softley C.Logarithmic number system and floating-point arithmetics on FPGA , Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream, p. 627-636 , Eds: Glesner M., Zipf P., Renovell M., Springer, (Berlin 2002) Lecture Notes in Computer Science. vol.2438 , International Conference FPL 2002 /12./, (Montpellier, FR, 02.09.2002-04.09.2002) [2002]
    33. Líčko Miroslav, Tichý Milan, Heřmánek Antonín, Matoušek Rudolf, Pohl ZdeněkPrototyping of DSP algorithms on FPGA , POSTER 2002, p. 2, FEL ČVUT, (Praha 2002) , International Student Conference on Electrical Engineering /6./, (Praha, CZ, 23.05.2002) [2002]
    34. Kadlec Jiří, Tichý Milan, Heřmánek Antonín, Pohl Z., Líčko M.Matlab Toolbox for high-level bit-exact emulation of HandelC VHDL FPGA designs , Design, Automation and Test in Europe DATE˙02, p. 264 , Eds: Sciuto D., Kloos C. D., IEEE, (Los Alamitos 2002) , Design, Automation and Test in Europe DATE˙02, (Paris, FR, 04.03.2002-08.03.2002) [2002]
    35. Matoušek R., Pohl Z., Kadlec Jiří, Tichý Milan, Heřmánek AntonínLogarithmic arithmetic core based RLS LATTICE implementation , Design, Automation and Test in Europe DATE 02, p. 271 , Eds: Sciuto D., Kloos C. D., IEEE, (Los Alamitos 2002) , Design, Automation and Test in Europe DATE 02, (Paris, FR, 04.03.2002-08.03.2002) [2002]
    36. Tichý Milan, Kovář BohumilParallel factorised algorithms for mixture estimation , Artificial Neural Nets and Genetic Algorithms. Proceedings, p. 410-413 , Eds: Kůrková V., Neruda R., Kárný M., Steele M. C., Springer, (Wien 2001) , International Conference on Artificial Neural Networks and Genetic Algorithms /5./, (Praha, CZ, 22.04.2001-25.04.2001) [2001]
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