Reducing Power Consumption of an Embedded DSP Platform through the Clock-Gating Technique

Conference Paper (international conference)

Heřmánek Antonín, Kuneš Michal, Tichý Milan

serial: Proceedings of the International Conference on Field Programmable Logic and Applications

action: 20th International Conference on Field Programmable Logic and Applications, (Milano, IT, 31.08.2010-02.09.2010)

research: CEZ:AV0Z10750506

project(s): 7H09005, GA MŠk

keywords: FPGA, Clock Gating, Digital design, System on Chip, Multicore Embedded System, Power consumption

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abstract (eng):

The paper describes application of the clock-gating techniques, often used in ASIC designs, to the field of FPGAbased systems. The clock-gating techniques are used to reduce the total power of the system. To achieve this, we reduce clock power consumption of the system by switching-off the clock signal for the parts of system that are not used. The system presented in this paper is based on the main processor, extended with several reconfigurable accelerators. These accelerators extend the processor capabilities by several vector operations and can be reprogrammed in run-time. Clock gating, in our design, is used to switch the accelerators off when not used. As the accelerators can represent a major part of the system size, switching them off can significantly reduce the power consumption. We also propose the method for estimation of the reduction of power consumption that can be achieved using the clock-gating technique.

RIV: JA