The LD-RLS algorithm with directional forgetting implemented on a vector-like hardware accelerator

Conference Paper (international conference)

Bartosinski Roman

serial: ICASSP 2011: IEEE International Conference on Acoustics, Speech, and Signal Processing

action: ICASSP 2011: IEEE International Conference on Acoustics, Speech, and Signal Processing, (Praha, CZ, 22.05.2011-27.05.2011)

research: CEZ:AV0Z10750506

project(s): JU100230 Artemis, GA MŠk, 7H10001, GA MŠk

keywords: LDU decomposition, directional forgetting, hardware accelerator

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abstract (eng):

The paper discusses an RLS algorithm based on the LDU decomposition (LD-RLS) with directional forgetting implemented on an embedded system with a vector-oriented hardware accelerator. The LD-RLS algorithm can be attractive for control applications to identify an unknown system or to track time-varying parameters. A solution of the LD-RLS algorithm directly contains the estimated parameters. It also offers a possibility to use a priori information about the identified system and its parameters. The implementation of the LD-RLS algorithm is done on an FPGA-based accelerator from a high-level abstraction. It is compared with an implementation of the same algorithm in software on the same platform.

RIV: IN