Extension for Xilinx System Generator - logarithmic arithmetic blockset

Conference Paper (international conference)

Líčko Miroslav, Métais B., Tichý Milan, Matoušek Rudolf

serial: MATLAB 2002. Sborník příspěvků 10. ročníku konference, p. 280-284

publisher: VŠCHT, (Praha 2002)

action: MATLAB 2002, (Praha, CZ, 07.11.2002)

research: CEZ:AV0Z1075907

project(s): LN00B096, GA MŠk

keywords: Xilinx System Generator, field programmable gate arrays, MATLAB/Simulink

abstract (eng):

The paper introduces support of floating point(FP) data format for the Xilinx System Generator (XSG) using logarithmic arithmetic. This type of arithmetic seems to be one of the promising ways to solve FP sort of DSP problems in practice. Our 32-bit high-speed logarithmic arithmetic (HSLA) keeps the accuracy according to IEEE 754 and speed up some kinds of FP algorithms. Promising is 19-bit equivalent utilised int this paper. It offers reasonable precision for the practical use and has min.HW requirements.

Cosati: 09H, 09G

RIV: JC