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Bibliografie

1ET300750402

  1. Kloub JanArchitektura systému pro dynamicky rekonfigurovatelný komunikační terminál , Počítačové architektury a diagnostika 2008 Sborník příspěvků, p. 51-56 , Eds: Plíva Zdeněk, Novák Ondřej, Jeníček Jiří, Rozkovec Martin, Počítačové architektury a diagnostika 2008, (Hejnice, CZ, 15.09.2008-17.09.2008) [2008] Download
  2. Kloub Jan, Heřmánek AntonínAkcelerátor pro dekódování konvolučního a Reed-Solomonova zabezpečovacího kódu , Technical computing Prague 2007. 15th annual conference proceedings, p. 74-74, Technical computing Prague 2007. 15th annual conference, (Praha, CZ, 14.11.2007-14.11.2007) [2007]
  3. Mazanec TomášSimulator of ADSL Physical Layer , Technical computing Prague 2007. 15th annual conference proceedings, p. 1-10, Technical computing Prague 2007. 15th annual conference, (Praha, CZ, 14.11.2007-14.11.2007) [2007]
  4. Mazanec Tomáš, Heřmánek AntonínADSL - ekvalizační techniky, ÚTIA, (Praha 2007) Research Report 2184 [2007]
  5. Pohl ZdeněkKomunikace pro adm-xrc-4sx, ÚTIA AV ČR, (Praha 2007) [2007]
  6. Šůcha P., Hanzálek Z., Heřmánek Antonín, Schier JanEfficient FPGA Implementation of Equalizer for Finite Interval Constant Modulus Algorithm , IEEE Symposium on Industrial Embedded Systems - IES 2006, Proceedings of, p. 1-10, IEEE Symposium on Industrial Embedded Systems - IES 2006, (Antibes Juan-Les-Pins, FR, 18.10.2006-20.10.2006) [2006]
  7. Mazanec TomášAdvanced Algorithms for Equalization on ADSL Channel , Technical computing Prague 2006. 14th annual conference proceedings, p. 68-75 , Eds: Procházka A., Technical computing Prague 2006 /14./, (Prague, CZ, 26.10.2006) [2006]
  8. Heřmánek Antonín, Schier Jan, Šůcha P., Hanzálek Z.Optimization of finite interval CMA implementation for FPGA , Proceedings of the IEEE Workshop on Signal Processing Systems. SiPS 2005, p. 1-6, SiPS 2005. IEEE Workshop on Signal Processing Systems, (Athens, GR, 02.11.2005-04.11.2005) [2005]
  9. Heřmánek Antonín, Schier JanFPGA implementation of Finite Interval CMA , Proceedings of the first annual IEEE BENELUX/DSP Valley Signal Processing Symposium. SPS-DARTS 2005, p. 97-100, IEEE, (Antverpy 2005) , SPS-DARTS 2005 Signal Processing Symposium /1./, (Antverpy, BE, 19.04.2005-20.04.2005) [2005]
  10. Pohl Zdeněk, Kadlec Jiří, Šůcha P., Hanzálek Z.Performance tuning of interative algorithms in signal processing , Proseedings of the 2005 International Conference on Field Programmable Logic and Applications. FPL 2005, p. 699-702 , Eds: Rissa T., Wilton S., Leong P., FPL 2005. International Conference on Field Programmable Logic and Applications, (Tampere, FI, 24.08.2005-26.08.2005) [2005]
  11. Schier Jan, Heřmánek AntonínUsing logarithmic arithmetic to implement the Recursive Least Squares (QR) algorithm in FPGA , Field-Programmable Logic and Applications. 14th International Conference FPL 2004. Proceedings, p. 1149-1151, International Conference FPL 2004 /14./, (Antverp, BE, 30.08.2004-01.09.2004) [2004]
  12. Heřmánek Antonín, Schier Jan, Regalia P.Architecture design for FPGA implementation of finite interval CMA , Proceedings of the 12th European Signal Processing Conference, p. 1-4 , Eds: Hlawatsch F., Matz G., Rupp M., EUSIPCO 2004 /12./, (Vienna, AT, 06.09.2004-10.09.2004) [2004]