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33544
Pohl Zdeněk
:
Logarithmic number system and floating-point arithmetics an FPGA
,
Počítačové Architektury & Diagnostika PAD 2003, p. 9-16
, Eds: Kotásek Z., Růžička R., Sekanina L.,
VUT,
(Brno 2003)
,
PAD 2003 Počítačové Architektury & Diagnostika,
(Zvíkovské Podhradí, CZ, 24.09.2003-26.09.2003) [2003]
Albu F., Kadlec Jiří, Coleman N., Fagan A.
:
The Gauss-Seidel Fast Affine Projection algorithm
,
IEEE Workshop on Signal Processing Systems. Proceedings, p. 109-114
, Eds: Parhi K., Shanbhag N.,
IEEE,
(San Diego 2002)
,
SIPS 2002,
(San Diego, US, 16.10.2002-18.10.2002) [2002]
Albu F., Kadlec Jiří, Heřmánek Antonín, Fagan A., Coleman N.
:
Analysis of the LNS implementation of the fast affline projection algorithms
,
Proceedings of the Irish Signals and Systems Conference 2002. ISSC 2002, p. 251-255
, Eds: Marnane W., Lightbody G., Pesch D.,
Institute of Technology,
(Cork 2002)
,
Irish Signals and Systems Conference 2002,
(Cork, IE, 25.06.2002-26.06.2002) [2002]
Albu F., Kadlec Jiří, Coleman N., Fagan A.
:
Pipelined implementations of the A Priory Error-Feedback LSL algorithm using logarithmic arithmetic
,
Proceedings of the IEEE International Conference on Acoustics, Speech and Signal Processing, p. 2681-2684,
IEEE,
(Orlando 2002)
,
ICASSP 2002,
(Orlando, US, 13.05.2002-17.05.2002) [2002]
Matoušek Rudolf, Líčko Miroslav, Heřmánek Antonín, Softley C.
:
Floating-Point-Like Arithmetic for FPGA
,
POSTER 2002, p. 2,
FEL ČVUT,
(Praha 2002)
,
International Student Conference on Electrical Engineering /6./,
(Praha, CZ, 23.05.2002) [2002]
Matoušek Rudolf, Tichý Milan, Pohl Zdeněk, Kadlec Jiří, Softley C.
:
Logarithmic number system and floating-point arithmetics on FPGA
,
Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream, p. 627-636
, Eds: Glesner M., Zipf P., Renovell M.,
Springer,
(Berlin 2002)
Lecture Notes in Computer Science. vol.2438 ,
International Conference FPL 2002 /12./,
(Montpellier, FR, 02.09.2002-04.09.2002) [2002]
Kadlec Jiří, Tichý Milan, Heřmánek Antonín, Pohl Z., Líčko M.
:
Matlab Toolbox for high-level bit-exact emulation of HandelC VHDL FPGA designs
,
Design, Automation and Test in Europe DATE˙02, p. 264
, Eds: Sciuto D., Kloos C. D.,
IEEE,
(Los Alamitos 2002)
,
Design, Automation and Test in Europe DATE˙02,
(Paris, FR, 04.03.2002-08.03.2002) [2002]