Heřmánek Antonín, Schier Jan
:
FPGA implementation of Finite Interval CMA
, Proceedings of the first annual IEEE BENELUX/DSP Valley Signal Processing Symposium. SPS-DARTS 2005, p. 97-100, IEEE,
(Antverpy 2005)
, SPS-DARTS 2005 Signal Processing Symposium /1./,
(Antverpy, BE, 19.04.2005-20.04.2005) [2005]
Líčko Miroslav, Schier Jan
:
FPGA Prototyping Using Extensions to MATLAB/Simulink
, UK ACM SIGDA 3rd Workshop on Electronic Design Automation, p. 1-3
, Eds: Hettiaratchi S., University of Southampton,
(Southampton 2003)
, UK ACM SIGDA Workshop on Electronic Design Automation /3./,
(Southampton, GB, 11.09.2003-12.09.2003) [2003]
Líčko Miroslav, Schier Jan, Tichý Milan, Kühl M.
:
MATLAB/Simulink based methodology for rapid-FPGA-prototyping
, Field-Programmable Logic and Applications. Proceedings of the 13th International Conference, p. 984-987
, Eds: Cheung P. Y. K., Constantinides G. A., de Sousa J. T., Springer,
(Berlin 2003)
Lecture Notes in Computer Science. vol.2778 , Field-Programmable Logic and Applications /13./,
(Lisabon, PT, 01.09.2003-03.09.2003) [2003]
Schier Jan
:
Fast fixed-point algorithm for estimation of the system time lag
, Preprints of the 3rd European IEEE Workshop on Computer-Intensive Methods in Control and Data Processing, p. 151-154
, Eds: Rojíček J., Valečková M., Kárný M., Warwick K., ÚTIA AV ČR,
(Praha 1998)
, CMP'98 /3./,
(Praha, CZ, 07.09.1998-09.09.1998) [1998]
Schier Jan
:
A systolic algorithm for block-regularized RLS identification
, Algorithms and Parallel VLSI Architectures III, p. 49-60
, Eds: Moonen M., Catthor F., Elsevier,
(Amsterdam 1994)
, Algorithms and Parallel VLSI Architectures /3./,
(Leuven, BE, 29.08.1994-31.08.1994) [1994]
Schier Jan
:
The systolic regularized linear quadratic controller
, Computer-Intensive Methods in Control and Signal Processing, p. 133-140
, Eds: Kulhavá L., Kárný M., Warwick K., ÚTIA AV ČR,
(Praha 1994)
, IEEE Workshop CMP '94,
(Praha, CZ, 07.09.1994-09.09.1994) [1994]