Ústav teorie informace a automatizace

Jste zde

Bibliografie

Conference Paper (international conference)

A Survey of Hardware Technologies for Mixed-Critical Integration Explored in the Project EMC2

Isakovic H., Grosu R., Ratasich D., Kadlec Jiří, Pohl Zdeněk, Kerrison S.

: Computer Safety, Reliability, and Security : SAFECOMP 2017 Workshops, ASSURE, DECSoS, SASSUR, TELERISE, and TIPS, p. 127-140 , Eds: Tonetta Stefano, Schoitsch Erwin, Bitsch Friedemann

: SAFECOMP 2017 International Conference on Computer Safety, Reliability, and Security, (Trento, IT, 20170912)

: 7H14005, GA MŠk

: asymmetric multiprocessing, Network-on-Chip, Time-of-Flight sensor, multi-core architectures

: 10.1007/978-3-319-66284-8

: http://library.utia.cas.cz/separaty/2017/ZS/kadlec-0479509.pdf

(eng): Technologies described in the paper provide hardware solution from architectural level up to the peripheral and application specific hardware. Moreover paper presents extendable multiprocessing hardware platform based on Zynq hybrid SoC, an asymmetric multiprocessing in video processing architecture, Time-of-Flight sensor and image processing architecture, predictable and verifiable Network-on-Chip (NoC), heterogeneous time-triggered NoC architecture, virtual hardware platform, software-driven energy consumption optimization techniques, and time-predictable L1 cache memory. The application of hybrid SoC platforms opposed to COTS multi-core architecture provides multiple benefits and can be seen as a viable bridging solution in the gap between single- and multi-core architectures.

: JC

: 20206

07.01.2019 - 08:39