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Department of Signal Processing

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266052216
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Publications ÚTIA

SP Logo Our group focuses on the research, development and implementation of advanced digital signal and image processing algorithms, mainly in the fields of telecom, audio processing and scene analysis (image segmentation, motion detection). We build on our experience with the Bayesian approach to recursive identification of linear systems with time variable parameters.

Our target platforms are Field-Programmable Gate Arrays (FPGAs). We are focused mostly on embedded SoC solutions based on Xilinx Kintex, Zynq and ZynqULTRASCALE+ devices programmed by Xilinx Vivado and SDSoC tools. We also use Matlab/Simulink or OpenCV library to specify, model and verify algorithms which we subsequently convert and synthesize to FPGAs using HLS tools. That is why we also study features which result in fast execution, small memory footprint, small chip area and low power consumption. This is achieved through designing new DSP algorithms or modifying the existing DSP algorithms and by exploiting advanced architectural properties of FPGA circuits. Our aim is not only to deal with the theoretical design of algorithms but also to help industrial partners to solve implementation issues in all their complexity.

Currently we focus our development mainly around Zynq and ZynqULTRASCALE+ FPGA family boards from Xilinx and from Trenz (industrial and automotive grade ones).

Our aim is not only to deal with the theoretical design of algorithms but also to help industrial partners to solve implementation issues in all their complexity. The key partner is Technical Development of SKODA AUTO a.s. where we have main competence in development electronic systems for testing Human-Machine-Interface.

The department also continues in developing methods of Bayesian statistics towards estimation of mixtures with different distribution of components. The theory is used in practical applications (The Municipality of the capital city Prague, Motol University Hospital) and also lectured in Faculty of Transportation Sciences CTU, Prague.

Our department participated in several RTD projects supported by Framework Programmes of the EU as well as national grant agencies. Nowadays our group takes part in RTD projects financed by ECSELJoint Undertaking.

Among further activities belongs e.g. long-term participation in development international technical standards in Working Groups ISO.

See presentations and videos for the Department of Signal Processing evaluation 9th March 2021.

Submitted by admin on
Ing. Jiří Kadlec CSc.
Mgr. Milada Kadlecová
Ing. Lukáš Kohout
Ing. Raissa Likhonina Ph.D.
Ing. Radim Matulík
Doc. Ing. Ivan Nagy CSc.
Dr. Ing. Jiří Plíhal
Ing. Zdeněk Pohl Ph.D.
Tetiana Reznychenko
Doc. Ing. Evženie Uglickich CSc.
Ing. Raissa Likhonina from the Department of Signal Processing (ZS) received the Dean's prize of the Faculty of Transportation Sciences in the Students category of the 13th annual nationwide competition Czech traffic infrastructure / technology / innovation of the year 2015 for her diploma thesis Numerical simulation of impact with barries.
Článek "Instruction Set Extensions for Multi-Threading in LEON3" presentovaný na konferenci DDECS 2010, IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, získal ocenění za nejlepší příspěvek v oblasti číslicového návrhu. Cena byla předána během letošního ročníku konference DDECS 2011, pořádaného ve dnech 13.–14.4.2011 v Německu.
Naši kolegové Jan Schier a Bohumil Kovář získali Cenu za nejlepší článek (Best paper award) za svůj příspěvek Automated counting of yeast colonies using the Fast Radial Transform algorithm, prezentovaný na konferenci BIOINFORMATICS 2011, the International Conference on Bioinformatics Models, Methods and Algorithms, pořádané ve dnech 26. - 29. 1.
Tetiana Reznychenko

UrbanSmartPark project final event will be organized on December 9 and 16, 2020. You can see live demonstration of automated on-street parking and services in the harbor area as well as the conception and provision of parking services. 

After 15 years the most prominent European conference on programmable logic comes back to the Czech Republic. Organized by UTIA with the help of other major Czech universities active in this area, it will take place in Prague from August 31 to September 2, 2009.
For more details visit the main conference web site at http://fpl.org.