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Ing. Jiří Kadlec, CSc.

Head of the department
Research interests
Recursive system identification algorithms suitable for FPGA; rapid prototyping of advanced signal processing algorithms; Scalable floating point arithmetic for FPGA SoC designs
Publications ÚTIA
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The main aim of the EECONE project is to reduce e-waste on a European scale. The environmental impact arising from e-waste can thus be reduced by working in three principal areas: 1) Increase service…
The main objective of the storAIge project is the development and industrialization of FDSOI 28nm and next generation embedded Phase Change Memory (ePCM) world-class semiconductor technologies,…
Arrowhead Tools is Europe's largest project for solutions in automation and digitization for the industry. The purpose of the three-year project Arrowhead Tools is to create engineering tools…
The objective of FitOptiVis is to develop a cross-domain approach for smart integration of image- and video-processing pipelines for CPS covering a reference architecture, supported by low-power,…
The WAKEMEUP project objective is to set-up a pilot line for advanced microcontrollers with embedded non-volatile memory, design and manufacturing for the prototyping of innovative applications for…
SILENSE is an ECSEL JU standard (RIA) project. The SILENSE project will focus on using smart acoustic technologies and ultrasound in particular for Human Machine- and Machine to Machine Interfaces.…
Productive4.0 is one of the first Lighthouse projects funded under the ECSEL Joint Undertaking. The main aim is to create a user platform across value chains and industries, that especially promotes…
OKO ICT Branch Contact Organization gives support to research teams from universities, research institutes, IT companies wishing to participate in the FP7 Information and Communication Technologies (…
Ing. Roman Bartosinski Ph.D.
Ing. Petr Honzík Ph.D.
Ing. Zdeněk Pohl Ph.D.