Head of the department:
Jiří Kadlec

Deputy head of the department:
Zdenek Pohl

Secretary:
Milada Kadlecová

Contact information:
phone: +420 266 052 216
www: http://sp.utia.cz/
staff: people, Ph.D. students
List of publications, courses, projects

Our group focuses on the research, development and implementation of advanced digital signal and image processing algorithms, mainly in the fields of telecom, audio processing and scene analysis (image segmentation, motion detection). We build on our experience with statistical methods and with the relevant methods of linear algebra, namely on the experience with the Bayesian approach to system identification and modelling.

Our target platforms are Field- Programmable Gate Arrays (FPGAs) and Digital Signal Processors (DSPs). We use mostly Matlab/Simulink to specify, model and verify algorithms which we subsequently convert and synthesize to HW. As such specialized solutions are likely to be used in embedded systems, we also research features which result in fast execution, use small memory footprint, small chip area and have low power consumption. This is achieved through designing new or modifying the existing DSP algorithms on one hand and by exploiting advanced architectural properties such as dynamic reconfiguration of an FPGA on the other hand.

Our aim is not only to deal with the theoretical design of algorithms but also to help industrial partners to solve implementation issues in all their complexity. The state-of-the-art DSP applications, such as wireless networking, mobile communications or audio enhancement systems, are used very often as components in embedded systems. Roughly speaking, this means that such applications are implemented by means of rather limited hardware resources on a dedicated chip. Naturally, the implementation has to respect specifics of the target environment, e.g. limited memory, chip area and low power consumption.

The above-mentioned issues definitely call for a multidisciplinary approach. Typical embedded systems which we deal with are Field-Programmable Gate Arrays (FPGAs) or Digital Signal Processors (DSPs). We are currently developing advanced design tools linking the high-level design environments of Matlab/Simulink, Xilinx System Generator and VHDL with the tools for optimized physical design and for modular designs.

Our department has been participating in many research projects both on international and on the national level. For example, the ESPRIT project No. 33544 High- Speed Logarithmic Arithmetic Unit was aimed at implementing logarithmic arithmetic as an effective solution for the floating-point computations in embedded devices. The goal of the IST project RECONF2 - Design Methodology and Environment for Dynamic RECONFigurable FPGA was to develop design methodology for dynamic reconfiguration of the Xilinx and Atmel devices. In the frame of the IST project AETHER - Self-Adaptive Embedded Technologies for Pervasive Computing Architectures, we have explored possible applications of self-adaptation for more efficient design of complex embedded systems.

The aim of the FP7 project AppleCore was to extend the LEON2 processor with circuits to allow to switch between threads with minimum delay. Within the project Scalopes programme ARTEMIS JU), we have been designing mechanisms to reduce power consumption of the circuit. In the project SMECY we have been using our ÚTIA EdkDSP HW platform for acceleration of the floating point computations to develop complete chain of design tools for this platform, with application for acceleration of parallel algorithms for real-time signal and video processing. The goal of the project IDEAS (programme ENIAC JU) is to develop and verify the memory interface for system-on-chip applications for electric vehicles.

The scientific profile of our department is complemented with activities which promote cooperation between academia and industry. We have been engaged in several national as well as European suuport projects (Idealist, IST World, COSINE) which help local IT organizations to participate in large-scale projects within the ICT FP7 and joint technology initiatives programmes ARTEMIS and ENIAC.

 

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