Kafka Leoš
:
Analysis of Applicability of Partial Runtime Reconfiguration in Fault Emulator in Xilinx FPGAs
, Proceedings 2008 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, p. 178-181
, Eds: Straube Bernd, Drutarovský Miloš, Renovell Michel, Gramata Peter, Fischerová Mária, IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems. DDECS 2008 /11./,
(Bratislava, SK, 16.04.2008-18.04.2008) [2008]
Kafka Leoš, Novák O.
:
FPGA-based fault simulator
, Proceedings of the 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits adn Systems, p. 274-278
, Eds: Reorda M. S., Novák O., Straube B., DDECS 2006. IEEE Design and Diagnostics of Electronic Circuits and Systems,
(Prague, CZ, 18.04.2006-21.04.2006) [2006]
Kafka Leoš, Matoušek Rudolf
:
Design Retiming in HDL
, Proceedings of Workshop 2005, p. 258-259
, Eds: Říha B., ČVUT,
(Praha 2005)
, Annual University-Wide Seminar. WORKSHOP 2005 /13./,
(Praha, CZ, 21.03.2005-25.03.2005) [2005]
Kafka Leoš
:
An FPGA-based fault injector for TSC circuits
, Počítačové architektury a diagnostika, p. 77-81
, Eds: Lórencz R., Buček J., Zahradnický T., ČVUT FEL,
(Praha 2005)
, Počítačové architektury a diagnostika 2005. PAD 2005,
(Lázně Sedmihorky, CZ, 21.09.2005-23.09.2005) [2005]
Kafka Leoš, Kubalík P., Kubátová H., Novák O.
:
Fault classification for self-checking circuits implemented in FPGA
, Proceedings of the 8th IEEE Workshop on Design and Diagnostics of Electronics Circuits and Systems, p. 228-231
, Eds: Takách G., Hlawiczka A., Sziray J., University of West Hungary,
(Sopron 2005)
, IEEE Design and Diagnostics of Electronics Circuits and Systems Workshop /8./,
(Sopron, HU, 13.04.2005-16.04.2005) [2005]